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TPS40074 Datasheet

  • TPS40074

  • 具有電壓前饋的中等范圍輸入同步降壓控制器

  • 38頁(yè)

  • TI

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TPS40074
SLUS617 鈥?APRIL 2005
APPLICATION INFORMATION (continued)
INPUT VOLTAGE
vs
DBP VOLTAGE
10
V
DBP
鈭?/div>
Low Voltage Bypass Voltage
鈭?/div>
V
4.50
4.45
4.40
4.35
4.30
4.25
4.20
4.15
4.10
4.05
4.00
5
INPUT VOLTAGE
vs
LOW VOLTAGE BYPASS VOLTAGE
V
DBP
鈭?/div>
Driver Bypass Voltage
鈭?/div>
V
9
8
7
6
5
4
0
5
10
15
V
DD
鈭?/div>
Input Voltage
鈭?/div>
V
20
25
10
15
20
25
30
V
DD
鈭?/div>
Input Voltage
鈭?/div>
V
Figure 12.
Figure 13.
DIFFERENTIAL SENSE AMPLIFIER
The TPS40074 has an on board differential amplifier intended for use as a remote sensing amplifier for the
output voltage. Use of this amplifier for remote sensing eliminates load regulation issues due to voltage drops
that occur between the converter and the actual point of load. The amplifier is powered from the DBP pin and
can be used to monitor output voltages up to 6 V with a DBP voltage of 8 V. For lower DBP voltages, the sense
amplifier can be used to monitor output voltages up to 2-V below the DBP voltage. The internal resistors used to
configure the amplifier for unity gain match each other closely, but their absolute values can vary as much as
30%, so adding external resistance to alter the gain is not accurate in a production environment.
SYNCHRONIZATION
The SYNC pin accepts logic level signals and is used to synchronize the TPS40074 to an external clock source.
Synchronization occurs on the rising edge of the signal at the SYNC pin. There is a fixed delay of approximately
300 ns from the rising edge of the waveform at SYNC to the HDRV output turning on the high-side FET. The pin
may be left floating in this function is not used, or it may be connected to GND. The frequency of the external
clock must be greater than the free running frequency of the device as set by the resistor on the RT pin (R
RT
).
This pin requires a totem pole drive, or open collector/drain if pull up resistor to either LVBP or a separate supply
between 2.5 V and 5 V is used. Synchronization does not affect the modulator gain due to the voltage feed
forward circuitry. The programmable UVLO thresholds are affected by synchronization. The thresholds are
shifted by the ratio of the sync frequency to the free running frequency of the converter. For example,
synchronizing to a frequency 20% higher than the free running frequency results in the programmable UVLO
thresholds shifting up 20% from their calculated free run values. The synchronization frequency should be kept
less than 1.5 times the free run frequency for best performance, although higher multiples can be used.
POWERGOOD OPERATION
The PGD pin is an open drain output that actively pulls to GND if any of the following conditions are met
(assuming that the input voltage is above 4.5 V)
鈥?/div>
Soft-start is active (V
VSS
< 3.5 V)
鈥?/div>
V
FB
< 0.63 V
17

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