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TPS40074 Datasheet

  • TPS40074

  • 具有電壓前饋的中等范圍輸入同步降壓控制器

  • 348.00KB

  • 38頁

  • TI

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TPS40074
SLUS617 鈥?APRIL 2005
www.ti.com
APPLICATION INFORMATION (continued)
this scheme, the theoretical maximum output voltage that the converter can produce is approximately two times
the programmed startup voltage. For design, set the programmed startup voltage equal to or greater than the
desired output voltage divided by maximum duty cycle (85% for frequencies 500 kHz and below). For example, a
5-V output converter should not have a programmed startup voltage below 5.9 V.
Figure 8
shows the theoretical
maximum duty cycle (typical) for various programmed startup voltages
TYPICAL MAXIMUM DUTY CYCLE
vs
INPUT VOLTAGE
100
90
80
Duty Cycle
鈭?/div>
%
70
60
UVLO
(on)
= 4.5 V
50
40
30
20
UVLO
(on)
= 15 V
UVLO
(on)
= 8 V
UVLO
(on)
= 12 V
4
8
12
16
20
24
28
V
IN
鈭?/div>
Input Voltage
鈭?/div>
V
Figure 8.
Figure 9
shows the effect of changing input voltage on the duty cycle, and how that change takes place. The
pulse width modulator (PWM) ramp input is generated using a current that is proportional to the current into the
KFF pin. The TPS40074 holds this pin at a constant 400 mV, so connecting a resistor from KFF to the input
power supply causes a current to flow into the KFF pin that is proportional to the input voltage. The slope of the
ramp signal to the PWM is therefore proportional to the input voltage. This allows the duty cycle to change with
variations in Vin without requiring much response from the error amplifier, resulting in very good line transient
response. Another benefit is essentially constant PWM gain over the entire input voltage operating range. This
makes the output control loop easier to design for a wide input range converter.
12

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