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LT3470ETS8 Datasheet

  • LT3470ETS8

  • Micropower Buck Regulator with Integrated Boost and Catch Di...

  • 265.46KB

  • 16頁

  • Linear

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LT3470
APPLICATIO S I FOR ATIO
PCB Layout
For proper operation and minimum EMI, care must be
taken during printed circuit board layout. Note that large,
switched currents flow in the power switch, the internal
catch diode and the input capacitor. The loop formed by
these components should be as small as possible. Fur-
thermore, the system ground should be tied to the regu-
lator ground in only one place; this prevents the switched
current from injecting noise into the system ground.
These components, along with the inductor and output
capacitor, should be placed on the same side of the circuit
board, and their connections should be made on that layer.
Place a local, unbroken ground plane below these compo-
nents, and tie this ground plane to system ground at one
location, ideally at the ground terminal of the output
capacitor C2. Additionally, the SW and BOOST nodes
should be kept as small as possible. Unshielded inductors
can induce noise in the feedback path resulting in instabil-
ity and increased output ripple. To avoid this problem, use
vias to route the V
OUT
trace under the ground plane to the
feedback divider (as shown in Figure 5). Finally, keep the
FB node as small as possible so that the ground pin and
ground traces will shield it from the SW and BOOST nodes.
Figure 5 shows component placement with trace, ground
plane and via locations. Include vias near the GND pin of
the LT3470 to help remove heat from the LT3470 to the
ground plane.
SHDN
V
IN
C1
GND
VIAS TO FEEDBACK DIVIDER
VIAS TO LOCAL GROUND PLANE
OUTLINE OF LOCAL GROUND PLANE
Figure 5. A Good PCB Layout Ensures Proper, Low EMI Operation
3470f
12
U
Hot Plugging Safely
The small size, robustness and low impedance of ceramic
capacitors make them an attractive option for the input
bypass capacitor of LT3470. However, these capacitors
can cause problems if the LT3470 is plugged into a live
supply (see Linear Technology Application Note 88 for a
complete discussion). The low loss ceramic capacitor
combined with stray inductance in series with the power
source forms an under damped tank circuit, and the
voltage at the V
IN
pin of the LT3470 can ring to twice the
nominal input voltage, possibly exceeding the LT3470鈥檚
rating and damaging the part. If the input supply is poorly
controlled or the user will be plugging the LT3470 into an
energized supply, the input network should be designed to
prevent this overshoot. Figure 6 shows the waveforms
that result when an LT3470 circuit is connected to a 24V
supply through six feet of 24-gauge twisted pair. The first
plot is the response with a 2.2碌F ceramic capacitor at the
input. The input voltage rings as high as 35V and the input
current peaks at 20A. One method of damping the tank
circuit is to add another capacitor with a series resistor to
the circuit. In Figure 6b an aluminum electrolytic capacitor
has been added. This capacitor鈥檚 high equivalent series
resistance damps the circuit and eliminates the voltage
overshoot. The extra capacitor improves low frequency
ripple filtering and can slightly improve the efficiency of
the circuit, though it is likely to be the largest component
C2
V
OUT
3470 F05
W
U U

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