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ZL50233QCC Datasheet

  • ZL50233QCC

  • 4 Channel Voice Echo Cancellor

  • 37頁(yè)

  • ZARLINK   ZARLINK

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ZL50233
4 Channel Voice Echo Cancellor
Data Sheet
Features
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Independent multiple channels of echo
cancellation; from 4 channels of 64ms to 2
channels of 128ms with the ability to mix
channels at 128ms or 64ms in any combination
Independent Power Down mode for each group of
2 channels for power management
Fully compliant to ITU-T G.165, G.168 (2000) and
(2002) specifications
Passed AT&T voice quality testing for carrier
grade echo cancellers.
Compatible to ST-BUS and GCI interfaces with
2Mb/s serial PCM data
PCM coding,
碌/A-Law
ITU-T G.711 or sign
magnitude
Per channel Fax/Modem G.164 2100Hz or G.165
2100Hz phase reversal Tone Disable
Per channel echo canceller parameters control
Transparent data transfer and mute
Fast reconvergence on echo path changes
Fully programmable convergence speeds
Patented Advanced Non-Linear Processor with
high quality subjective performance
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Ordering Information
ZL50233/QCC 100-Pin LQFP
ZL50233/GDC 208-Ball LBGA
-40擄C to +85擄C
Protection against narrow band signal divergence
and instability in high echo environments
0 dB to -12 dB level adjusters (3 dB steps) at all
signal ports
Offset nulling of all PCM channels
10 MHz or 20 MHz master clock operation
3.3 V I/O pads and 1.8V Logic core operation with
5-Volt tolerant inputs
IEEE-1149.1 (JTAG) Test Access Port
ZL50232, ZL50233, ZL50234 and ZL50235 have
same pinouts in both LQFP and LBGA packages
March 2003
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Applications
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Voice over IP network gateways
Voice over ATM, Frame Relay
V
DD1 (3.3V)
V
SS
V
DD2 (1.8V)
ODE
Rin
Sin
MCLK
Fsel
Serial
to
Parallel
Echo Canceller Pool
Group 0
ECA/ECB
Parallel
to
Serial
Rout
Sout
Group 1
ECA/ECB
Note:
Refer to Figure 4
for Echo Canceller
block diagram
PLL
C4i
F0i
Timing
Unit
RESET
Microprocessor Interface
Test Port
DS CS R/W A10-A0 DTA
D7-D0 IRQ TMS TDI TDO TCK TRST
Figure 1 - ZL50233 Device Overview
1

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