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ZL50019 Datasheet

  • ZL50019

  • Enhanced 2 K Digital Switch with Stratum 4E DPLL

  • 858.29KB

  • 115頁

  • ZARLINK   ZARLINK

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ZL50019
Enhanced 2 K Digital Switch with
Stratum 4E DPLL
Data Sheet
Features
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2048 channel x 2048 channel non-blocking digital
Time Division Multiplex (TDM) switch at 8.192
and 16.384 Mbps or using a combination of ports
running at 2.048, 4.096, 8.192 and 16.384 Mbps
32 serial TDM input, 32 serial TDM output
streams
Integrated Digital Phase-Locked Loop (DPLL)
exceeds Telcordia GR-1244-CORE Stratum 4E
specifications
Output clocks have less than 1 ns of jitter (except
for the 1.544 MHz output)
DPLL provides holdover, freerun and jitter
attenuation features with four independent
reference source inputs
Exceptional input clock cycle to cycle variation
tolerance (20 ns for all rates)
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Ordering Information
ZL50019GAC 256-ball PBGA
ZL50019QCC 256-lead LQFP
-40擄C to +85擄C
Output streams can be configured as bi-
directional for connection to backplanes
Per-stream input and output data rate conversion
selection at 2.048, 4.096, 8.192 or 16.384 Mbps.
Input and output data rates can differ
Per-stream high impedance control outputs
(STOHZ) for 16 output streams
Per-stream input bit delay with flexible sampling
point selection
October 2004
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V
DD_CORE
V
DD_IO
V
DD_COREA
V
DD_IOA
V
SS
RESET
ODE
STi[31:0]
FPi
CKi
MODE_4M0
MODE_4M1
REF0
REF1
REF2
REF3
REF_FAIL0
REF_FAIL1
REF_FAIL2
REF_FAIL3
S/P Converter
Data Memory
P/S Converter
STio[31:0]
Input Timing
Connection Memory
Output HiZ
Control
STOHZ[15:0]
DPLL
Output Timing
FPo[3:0]
CKo[5:0]
FPo_OFF[2:0]
OSC_EN
OSC
Internal Registers &
Microprocessor Interface
Test Port
TDi
OSCo
DS_RD
R/W_WR
Figure 1 - ZL50019 Functional Block Diagram
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.
MOT_INTEL
DTA_RDY
D[15:0]
A[13:0]
OSCi
TRST
TMS
TCK
TDo
IRQ
CS

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