ZL50018QCC Datasheet

IC型號(hào)：
ZL50018QCC
PDF描述：
2 K Digital Switch with Enhanced Stratum 3 DPLL
文件大?。?/label>
1403.36KB
PDF頁(yè)數(shù)：
136頁(yè)
芯片廠家：
ZARLINK

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ZL50018

2 K Digital Switch with Enhanced

Stratum 3 DPLL

Data Sheet

Features

鈥?/div>

2048 channel x 2048 channel non-blocking digital

Time Division Multiplex (TDM) switch at 8.192

and 16.384 Mbps or using a combination of ports

running at 2.048, 4.096, 8.192 and/or

16.384 Mbps

32 serial TDM input, 32 serial TDM output

streams

Integrated Digital Phase-Locked Loop (DPLL)

exceeds Telcordia GR-1244-CORE Stratum 3

specifications

Output clocks have less than 1 ns of jitter (except

for the 1.544 MHz output)

DPLL provides holdover, freerun and jitter

attenuation features with four independent

reference source inputs

鈥?/div>

Ordering Information

ZL50018GAC

ZL50018QCC

256 Ball PBGA

256 Lead LQFP

Trays

July 2005

鈥?/div>

-40擄C to +85擄C

Programmable key DPLL parameters (filter corner

frequency, locking range, auto-holdover

hysteresis range, phase slope, lock detector

range)

Exceptional input clock cycle to cycle variation

tolerance (20 ns for all rates)

Output streams can be configured as bi-

directional for connection to backplanes

鈥?/div>

DD_CORE

DD_IO

DD_COREA

DD_IOA

RESET

ODE

STi[31:0]

FPi

CKi

MODE_4M0

MODE_4M1

REF0

REF1

REF2

REF3

REF_FAIL0

REF_FAIL1

REF_FAIL2

REF_FAIL3

S/P Converter

Data Memory

P/S Converter

STio[31:0]

Input Timing

Connection Memory

Output HiZ

Control

STOHZ[15:0]

DPLL

Output Timing

FPo[3:0]

CKo[5:0]

FPo_OFF[2:0]

OSC_EN

OSC

Internal Registers &

Microprocessor Interface

Test Port

TDi

OSCo

DS_RD

R/W_WR

Figure 1 - ZL50018 Functional Block Diagram

Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,

France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

MOT_INTEL

DTA_RDY

D[15:0]

A[13:0]

OSCi

TRST

TMS

TCK

TDo

IRQ

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