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ZL38002QDG1 Datasheet

  • ZL38002QDG1

  • Low-Voltage Acoustic Echo Canceller With Noise Reduction

  • 47頁

  • ZARLINK   ZARLINK

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ZL38002
Low-Voltage Acoustic Echo Canceller
with Noise Reduction
Data Sheet
Features
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112 ms acoustic echo canceller
Up to 12 dB of noise reduction
Works with low cost voice codec. ITU-T G.711 or
signed mag
碌/A-Law,
or linear 2鈥檚 compliment
Each port may operate independently in
companded format or linear format
Advanced NLP design - full duplex speech with
no switched loss on audio paths
Fast re-convergence time: tracks changing echo
environment quickly
Adaptation algorithm converges even during
Double-Talk
Designed for exceptional performance in high
background noise environments
Provides protection against narrow-band signal
divergence
Howling prevention stops uncontrolled oscillation
in high loop gain conditions
Programmable offset nulling of all PCM channels
Serial micro-controller interface
Idle channel noise suppression
ST-BUS, GCI, or variable-rate SSI PCM
interfaces
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Ordering Information
ZL38002QDG
48 Pin TQFP
ZL38002QDG1 48 Pin TQFP*
ZL38002DGA1 36 Pin QSOP*
ZL38002DGB1 36 Pin QSOP*
* Pb Free Matte Tin
-40擄C to 85擄C
User gain control provided for speaker path
(-24 dB to +21 dB in 3 dB steps)
Adjustable gain pads from -24 dB to +21 dB at
Xin, Sin and Sout to compensate for different
system requirements
AGC on speaker path
Handles up to -6 dB acoustic echo return loss
(with the appropriate gain pad settings)
Transparent data transfer and mute options
20 MHz master clock operation
Low power mode during PCM Bypass
Bootloadable for future factory software upgrades
2.7 V to 3.6 V supply voltage; 5 V-tolerant inputs
Trays
Trays
Tubes
Tape and Reel
August 2005
Limiter
Sin
MD1
NBSD
CONTROL
Adaptive
Filter
UNIT
Double
Talk
Detector
R
1
R
1
NBSD
Program
ROM
Program
RAM
碌
/A-Law/
Linear
HP
Filter
Gain
Pad
S
1
+
+
-
S
2
ADV
NLP
Noise
Reduction
Gain
Pad
Linear/
碌/A-Law
Sout
DATA1
DATA2
ACOUSTIC ECHO PATH
Micro
Interface
Gain
Pad
Howling
Controller
MD2
Rout
L
inear/
碌
/A-Law
Limiter
SCLK
-24 -> +21dB
CS
HP
Filter
碌
/A-Law/
Linear
AGC
User
Gain
Rin
VDD
VSS
RESET
FORMAT
ENA2
ENA1
LAW
F0i
BCLK/C4i
MCLK
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2005, Zarlink Semiconductor Inc. All Rights Reserved.

ZL38002QDG1 產品屬性

  • 0現(xiàn)貨

  • 在售

  • -

  • 托盤

  • 在售

  • 回聲消除

  • 串行

  • 1

  • 2.7V ~ 3.6V

  • 20mA

  • 90 mW

  • -40°C ~ 85°C

  • 表面貼裝型

  • 48-TQFP

  • 48-TQFP（7x7）

ZL38002QDG1相關型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    Low-Voltage Acoustic Echo Canceller with Low ERL Compensatio...
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  • 英文版
    Low-Voltage Acoustic Echo Canceller with Low ERL Compensatio...
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  • 英文版
    Low-Voltage Acoustic Echo Canceller With Noise Reduction
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  • 英文版
    Low-Voltage Acoustic Echo Canceller With Noise Reduction
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    AEC with Noise Reduction & Codecs for Digital Hands-Free Com...
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    Low-Voltage Acoustic Echo Canceller With Noise Reduction
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