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ZL38001DGA Datasheet

  • ZL38001DGA

  • Low-Voltage Acoustic Echo Canceller with Low ERL Compensatio...

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  • ZARLINK   ZARLINK

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ZL38001
Low-Voltage Acoustic Echo Canceller
with Low ERL Compensation
Data Sheet
Features
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Contains two echo cancellers: 112 ms acoustic
echo canceller
Works with low cost voice codec. ITU-T G.711 or
signed mag
碌/A-Law,
or linear 2鈥檚 comp
Each port may operate in different format
Advanced NLP design - full duplex speech with
no switched loss on audio paths
Fast re-convergence time: tracks changing echo
environment quickly
Adaptation algorithm converges even during
Double-Talk
Designed for exceptional performance in high
background noise environments
Provides protection against narrow-band signal
divergence
Howling prevention stops uncontrolled oscillation
in high loop gain conditions
Offset nulling of all PCM channels
Serial micro-controller interface
-40擄C to +85擄C
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ST-BUS, GCI, or variable-rate SSI PCM interfaces
User gain control provided for speaker path
(-24 dB to +48 dB in 3 dB steps)
18 dB gain at Sout to compensate for high ERL
environments
AGC on speaker path
Handles up to 0 dB acoustic echo return loss
Transparent data transfer and mute options
20 MHz master clock operation
Low power mode during PCM Bypass
Bootloadable for future factory software upgrades
2.7 V to 3.6 V supply voltage; 5 V-tolerant inputs
Ordering Information
ZL38001DGA
ZL38001QDC
36 Pin QSOP
48 Pin TQFP
June 2004
Limiter
Sin
MD1
NBSD
CONTROL
UNIT
Adaptive
Filter
Double
Talk
Detector
R
3
R
1
NBSD
Program
ROM
Program
RAM
碌
/A-Law/
Linear
Offset
Null
S
1
+
+
-
S
2
ADV
NLP
S
3
18dB
Gain
Linear/
碌/A-Law
Sout
DATA1
DATA2
ACOUSTIC ECHO PATH
LINE ECHO PATH
Micro
Interface
PORT 1
PORT 2
Howling
Controller
MD2
Rout
L
inear/
碌
/A-Law
Limiter
SCLK
-24 -> +48dB
CS
R
2
Offset
Null
碌
/A-Law/
Linear
AGC
User
Gain
Rin
VDD
VSS
RESET
FORMAT
ENA2
ENA1
LAW
F0i
BCLK/C4i
MCLK
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.

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