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Description
The ZL30409 T1/E1 System Synchronizer contains a
digital phase-locked loop (DPLL), which provides timing
and synchronization signals for multitrunk T1 and E1
primary rate transmission links.
The ZL30409 generates ST-BUS clock and framing
signals that are phase locked to either a 19.44 MHz,
2.048MHz, 1.544MHz, or 8kHz input reference.
OSCi
OSCo
TCLR
LOCK
V
DD
GND
Master Clock
TCK
TDI
TMS
TRST
TDO
PRI
SEC
IEEE
1149.1a
TIE
Corrector
Circuit
Selected
Reference
Reference
Select
MUX
Reference
Select
TIE
Corrector
Enable
Virtual
Reference
DPLL
Output
Interface
Circuit
State
Select
Input
Impairment
Monitor
State
Select
C19o
C1.5o
C2o
C4o
C6o
C8o
C16o
F0o
F8o
F16o
RSP
TSP
RSEL
Control State Machine
Feedback
Frequency
Select
MUX
MS1 MS2
RST
HOLDOVER PCCi FLOCK
FS1
FS2
Figure 1 - Functional Block Diagram
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.