音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

ZL30406QGC Datasheet

  • ZL30406QGC

  • SONET/SDH Clock Multiplier PLL

  • 21頁

  • ZARLINK   ZARLINK

掃碼查看芯片數(shù)據(jù)手冊(cè)

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

ZL30406
SONET/SDH Clock Multiplier PLL
Data Sheet
Features
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Meets jitter requirements of Telcordia GR-253-
CORE for OC-48, OC-12, and OC-3 rates
Meets jitter requirements of ITU-T G.813 for STM-
16, STM-4 and STM-1 rates
Provides four LVPECL differential output clocks at
77.76 MHz
Provides a CML differential clock programmable
to 19.44 MHz, 38.88 MHz, 77.76 MHz and
155.52 MHz
Provides a single-ended CMOS clock at
19.44 MHz
Provides enable/disable control of output clocks
Accepts a CMOS reference at 19.44 MHz
3.3 V supply
Ordering Information
ZL30406QGC
64 Pin TQFP
ZL30406QGC1 64 Pin TQFP*
*Pb Free Matte Tin
-40擄C to +85擄C
Trays
Trays
February 2005
Description
The ZL30406 is an analog phase-locked loop (APLL)
designed to provide rate conversion and jitter
attenuation for SDH (Synchronous Digital Hierarchy)
and SONET (Synchronous Optical Network)
networking equipment. The ZL30406 generates very
low jitter clocks that meet the jitter requirements of
Telcordia GR-253-CORE OC-48, OC-12, OC-3, OC-1
rates and ITU-T G.813 STM-16, STM-4 and STM-1
rates.
The ZL30406 accepts a CMOS compatible reference
at 19.44 MHz and generates four LVPECL differential
output clocks at 77.76 MHz, a CML differential
clock programmable to 19.44 MHz, 38.88 MHz,
77.76 MHz and 155.52 MHz and a single-ended
CMOS clock at 19.44 MHz. The output clocks can
be individually enabled or disabled.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Applications
鈥?/div>
鈥?/div>
SONET/SDH line cards
Network Element timing cards
LPF
C77oEN-A
C77oEN-B
OC-CLKoEN
C77o
,
C155o
C19o, C38o,
CML-P/N outputs
OC-CLKoP/N
C19i
Frequency
& Phase
Detector
19.44MHz
BIAS
Reference &
Bias circuit
Loop
Filter
Output
VCO
Interface
Circuit
C77oP/N-A
C77oP/N-B
C77oP/N-C
C77oP/N-D
C19o
VDD GND
VCC
FS1-2
C19oEN
C77oEN-C
C77oEN-D
15
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.

ZL30406QGC相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
    描述
    廠商
    下載
  • 英文版
    T1/E1 System Synchronizer
    ZARLINK
  • 英文版
    T1/E1 System Synchronizer
    ZARLINK [Z...
  • 英文版
    T1/E1 Stratum 3 System Synchronizer
    ZARLINK
  • 英文版
    T1/E1 Stratum 3 System Synchronizer
    ZARLINK [Z...
  • 英文版
    T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for D...
    ZARLINK
  • 英文版
    T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for D...
    ZARLINK [Z...
  • 英文版
    T1/E1/SDH Stratum 3 Redundant System Clock Synchonizer for A...
    ZARLINK
  • 英文版
    T1/E1/SDH Stratum 3 Redundant System Clock Synchonizer for A...
    ZARLINK [Z...
  • 英文版
    SONET/SDH/PDH Network Interface DPLL
    ZARLINK
  • 英文版
    SONET/SDH/PDH Network Interface DPLL
    ZARLINK [Z...
  • 英文版
    GbE Line Card Synchronizer
    ZARLINK [Z...
  • 英文版
    Network Interface DPLL
    ZARLINK
  • 英文版
    Network Interface DPLL
    ZARLINK [Z...
  • 英文版
    DS1/E1 System Synchronizer with 19.44 MHz Output
    ZARLINK
  • 英文版
    DS1/E1 System Synchronizer with 19.44 MHz Output
    ZARLINK [Z...
  • 英文版
    Telecom Rate Conversion DPLL
    ZARLINK [Z...
  • 英文版
    POTS Line Card PLL
    ZARLINK [Z...
  • 英文版
    SONET/SDH OC-48/OC-192 System Synchronizer
    ZARLINK [Z...
  • 英文版
    SONET/SDH OC-48/OC-192 Line Card Synchronizer
    ZARLINK [Z...
  • 英文版
    Low Jitter Line Card Synchronizer
    ZARLINK [Z...

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號(hào)，
第一時(shí)間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動(dòng)力！意見一經(jīng)采納，將有感恩紅包奉上哦！