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Supports Telcordia GR-1244-CORE Stratum 4 and

Stratum 4E

Supports ITU-T G.823 and G.824 for 2048 kbit/s and

1544 kbit/s interfaces

Supports ANSI T1.403 and ETSI ETS 300 011 for

ISDN primary rate interfaces

Simple hardware control interface

Accepts two input references and synchronizes to

any combination of 2 kHz, 8 kHz, 1.544 MHz,

2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz

inputs

Provides a range of clock outputs: 1.544 MHz,

2.048 MHz, 16.384 MHz, 19.44 MHz and either

4.096 MHz and 8.192 MHz or 32.768 MHz and

65.536 MHz

Provides 5 styles of 8 kHz framing pulses and a

2 kHz multi-frame pulse

Holdover frequency accuracy of 1.5 x 10

-7

Lock, Holdover and selectable Out of Range

indication

Selectable loop filter bandwidth of 1.8 Hz or 922 Hz

鈥?/div>

Ordering Information

ZL30109QDG 64 pin TQFP

-40擄C to +85擄C

Less than 24 ps

rms

intrinsic jitter on the

19.44 MHz output clock, compliant with OC-3 and

STM-1 jitter specifications

Less than 0.6 ns

pp

intrinsic jitter on all output

clocks

External master clock source: clock oscillator or

crystal

October 2004

鈥?/div>

Applications

鈥?/div>

Synchronization and timing control for DSLAM,

Gateway and PBX systems that require Stratum

4/4E timing

Line Card synchronization for SDH/PDH

applications

Clock and frame pulse source for ST-BUS, GCI

and other time division multiplex (TDM) buses

OSCi OSCo

Master Clock

REF0

REF1

MUX

TIE_CLR

BW_SEL LOCK

OUT_SEL

C2o

C4/C65o

C8/C32o

C16o

F4/F65o

F8/F32o

F16o

C1.5o

C19o

F2ko

TIE

Corrector

Circuit

Virtual

Reference

DPLL

E1

Synthesizer

REF_FAIL0

REF_FAIL1

OOR_SEL

Reference

Monitor

TIE

Corrector

Enable

Mode

Control

DS1

Synthesizer

Frequency

Select

MUX

SONET/SDH

Synthesizer

Feedback

REF_SEL

State Machine

RST

IEEE

1149.1a

TRST

MODE_SEL1:0

HMS

HOLDOVER

TCK TDI

TMS TDO

Figure 1 - Functional Block Diagram

1

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

型號(hào)

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描述

廠商

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