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ZL30105QDG Datasheet

  • ZL30105QDG

  • T1/E1/SDH Stratum 3 Redundant System Clock Synchonizer for A...

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ZL30105
T1/E1/SDH Stratum 3 Redundant System Clock
Synchonizer for AdvancedTCA鈩?and H.110
Data Sheet
Features
鈥?/div>
Synchronizes to clock-and-sync-pair to maintain
minimal phase skew between the master-clock
and the redundant slave-clock
Supports ITU-T G.813 option 1, G.823 for 2048 kbs
and G.824 for 1544 kbs interfaces
Supports Telcordia GR-1244-CORE Stratum
3/4/4E
Supports ANSI T1.403 and ETSI ETS 300 011 for
ISDN primary rate interfaces
Accepts three input references and synchronizes
to any combination of 2 kHz, 8 kHz, 1.544 MHz,
2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz
inputs
Provides a range of clock outputs: 1.544 MHz
(DS1), 2.048 MHz (E1), 3.088 MHz, 16.384 MHz,
and 19.44 MHz (SDH), and either 4.096 MHz and
8.192 MHz or 32.768 MHz and 65.536 MHz, and a
choice of 6.312 MHz (DS2), 8.448 MHz (E2),
44.736 MHz (DS3) or 34.368 MHz (E3)
Provides 5 styles of 8 kHz framing pulses and a
2 kHz multi-frame pulse
Holdover frequency accuracy of 1x10
-8
Selectable loop filter 1.8 Hz, 3.6 Hz or 922 Hz
Less than 20 ps
rms
intrinsic jitter on the 19.44 MHz
output clock, compliant with GR-253-CORE OC-3
and G.813 STM-1 specifications
OSCi
OSCo
TIE_CLR
June 2004
Ordering Information
ZL30105QDG
64 pin TQFP
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
-40擄C to +85擄C
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Less than 0.6 ns
pp
intrinsic jitter on all output
clocks and frame pulses
Manual or Automatic hitless reference switching
Provides Lock, Holdover and selectable Out of
Range indication
Simple hardware control interface
Selectable external master clock source: Clock
Oscillator or Crystal
鈥?/div>
Applications
鈥?/div>
Synchronization and timing control for multi-trunk
SDH and T1/E1 systems such as DSLAMs,
Gateways and PBXs
Clock and frame pulse source for
AdvancedTCA鈩? and other time division
multiplex (TDM) buses
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
FASTLOCK
LOCK
OUT_SEL2
Master Clock
REF0
REF1
REF2
REF2_SYNC
REF_FAIL0
REF_FAIL1
REF_FAIL2
TIE
Corrector
Enable
MUX
TIE
Corrector
Circuit
Virtual
Reference
DPLL
E1
Synthesizer
Reference
Monitor
DS1
Synthesizer
Mode
Control
SDH
Synthesizer
Programmable
Synthesizer
REF_SEL1:0
RST
State Machine
Frequency
Select
MUX
C2o
C4/C65o
C8/C32o
C16o
F4/F65o
F8/F32o
F16o
C1.5o
C3o
C19o
F2ko
C6/8.4/34/44o
OUT_SEL1:0
IEEE
1149.1a
TRST
MODE_SEL1:0
HMS
HOLDOVER
SEC_MSTR
APP_SEL1:0
TCK
TDI TMS TDO
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.

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