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ZL10312UBH Datasheet

  • ZL10312UBH

  • Satellite Demodulator

  • 15頁

  • ZARLINK   ZARLINK

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ZL10312
Satellite Demodulator
Data Sheet
Features
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Conforms to EBU specification for DVB-S and
DirecTV specification for DSS
On-chip digital filtering supports 1 - 45 MSps
symbol rates
On-chip 60 or 90 MHz dual-ADC
High speed scanning mode for blind symbol
rate/code rate acquisition
Automatic spectral inversion resolution
High level software interface for minimum
development time
Up to 鹵22 MHz LNB frequency tracking
DiSEqC鈩?v2.2: receive/transmit for full control of
LNB, dish and other components
Compact 64 pin LQFP package (7 x 7 mm)
Sleep pin gives ~1,000 fold reduction in power to
help products meet ENERGY STAR
廬
requirements
ZL10312QCG
ZL10312QCF
ZL10312QCG1
ZL10312UBH
November 2004
Ordering Information
64 Pin LQFP
64 Pin LQFP
64 Pin LQFP*
Die supplied in
Trays, Bake & Drypack
Tape & Reel
Trays, Bake & Drypack
wafer form**
*Pb Free Matte Tin
**
Please contact Sales for further details
0擄C to +70擄C
Description
The ZL10312 is a QPSK/BPSK 1 - 45 MSps
demodulator and channel decoder for digital satellite
television transmissions to the European Broadcast
Union ETS 300 421 specification. It receives analogue
I and Q signals from the tuner, digitises and digitally
demodulates this signal, and implements the complete
DVB/DSS FEC (Forward Error Correction), and de-
scrambling function. The output is in the form of
MPEG2 or DSS transport stream data packets. The
ZL10312 also provides automatic gain control to the RF
front-end device.
The ZL10312 has a serial 2-wire bus interface to the
control microprocessor. Minimal software is required to
control the ZL10312 because of the built in automatic
search and decode control functions.
Applications
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DVB 1 - 45 MSps compliant satellite receiver
DSS 20 MSps compliant satellite receivers
SMATV trans-modulators. (Single Master
Antenna TV)
Satellite PC applications
I I/P
Dual ADC
Q I/P
De-rotator
Decimation
Filtering
Timing recovery
Matched filter
Phase recovery
DVB
DSS
FEC
MPEG/
DSS
Packets
Analog
AGC
Control
Clock Generation
Acquisition
Control
2-Wire Bus
Interface
Bus I/O
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved.

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