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Z8S18020PSC Datasheet

  • Z8S18020PSC

  • ENHANCED Z180 MICROPROCESSOR

  • 386.23KB

  • 70頁(yè)

  • ZILOG   ZILOG

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P
RELIMINARY
P
RODUCT
S
PECIFICATION
1
Z80180/Z8S180/
Z8L180 SL1919
E
NHANCED
Z180 M
ICROPROCESSOR
FEATURES
s
s
s
s
s
s
s
s
s
1
Code Compatible with Zilog Z80
廬
CPU
Extended Instructions
Two Chain-Linked DMA Channels
Low Power-Down Modes
On-Chip Interrupt Controllers
Three On-Chip Wait-State Generators
On-Chip Oscillator/Generator
Expanded MMU Addressing (up to 1 MB)
Clocked Serial I/O Port
s
s
s
s
s
s
s
Two 16-Bit Counter/Timers
Two Enhanced UARTs (up to 512 Kbps)
Clock Speeds: 6, 8, 10, 20, 33 MHz
Operating Range: 5V (3.3V@ 20 MHz)
Operating Temperature Range: 0
擄
C to +70
擄
C
-40
擄
C to +85
擄
C Extended Temperature Range
Three Packaging Styles
鈥?68-Pin PLCC
鈥?64-Pin DIP
鈥?80-Pin QFP
GENERAL DESCRIPTION
The enhanced Z80180/Z8S180/Z8L180
鈩?/div>
significantly im-
proves on the previous Z80180 models while still providing
full backward compatibility with existing Zilog Z80 devices.
The Z80180/Z8S180/Z8L180 now offers faster execution
speeds, power saving modes, and EMI noise reduction.
This enhanced Z180 design also incorporates additional
feature enhancements to the ASCIs, DMAs, and I
cc
STANDBY Mode power consumption. With the addition of
鈥淓SCC-like鈥?Baud Rate Generators (BRGs), the two ASCIs
now have the flexibility and capability to transfer data asyn-
chronously at rates of up to 512 Kbps. In addition, the ASCI
receiver has added a 4-byte First In First Out (FIFO) which
can be used to buffer incoming data to reduce the inci-
dence of overrun errors. The DMAs have been modified to
allow for a 鈥渃hain-linking鈥?of the two DMA channels when
set to take their DMA requests from the same peripherals
device. This feature allows for non-stop DMA operation be-
tween the two DMA channels, reducing the amount of CPU
intervention (Figure 1).
Not only does the Z80180/Z8S180/Z8L180 consume less
power during normal operations than the previous model,
it has also been designed with three modes intended to fur-
ther reduce the power consumption. Zilog reduced I
cc
pow-
er consumption during STANDBY Mode to a minimum of
10
碌
A by stopping the external oscillators and internal
clock. The SLEEP mode reduces power by placing the
CPU into a 鈥渟topped鈥?state, thereby consuming less cur-
rent while the on-chip I/O device is still operating. The
SYSTEM STOP mode places both the CPU and the on-
chip peripherals into a 鈥渟topped鈥?mode, thereby reducing
power consumption even further.
A new clock doubler feature has been implemented in the
Z80180/Z8S180/Z8L180 device that allows the program-
mer to double the internal clock from that of the external
clock. This provides a systems cost savings by allowing
the use of lower cost, lower frequency crystals instead of
the higher cost, and higher speed oscillators.
The Enhanced Z180 is housed in 80-pin QFP, 68-pin
PLCC, and 64-pin DIP packages.
DS971800401
PRELIMINARY
1-1

Z8S18020PSC 產(chǎn)品屬性

  • 8

  • 集成電路 (IC)

  • 嵌入式 - 微處理器

  • Z180

  • Z80

  • 增強(qiáng)型 Z180

  • 20MHz

  • 5V

  • 通孔

  • 64-DIP（0.750"，19.05mm）

  • 64-DIP

  • 管件

  • 269-3107

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