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XRT79L71 Datasheet

  • XRT79L71

  • 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

  • 4051.54KB

  • 441頁

  • EXAR   EXAR

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謾莽
JUNE 2003
PRELIMINARY
鈥?/div>
JTAG Interface
L
INE
I
NTERFACE
U
NIT
XRT79L71
REV. P1.0.3
1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
GENERAL DESCRIPTION
The XRT79L71 is a single channel, ATM UNI/PPP
Physical Layer Processor with integrated DS3/E3
framing controller and Line Interface Unit with Jitter
Attenuator that is designed to support ATM direct
mapping and cell delineation as well as PPP mapping
and Frame processing. For ATM UNI applications,
this device provides the ATM Physical Layer (Physical
Medium Dependent and Transmission Convergence
sub-layers) interface for the public and private net-
works at DS3/E3 rates. For Clear-Channel Framer
applications, this device supports the transmission
and reception of 鈥渦ser data鈥?via the DS3/E3 payload.
The XRT79L71 includes DS3/E3 Framing, Line
Interface Unit with Jitter Attenuator that supports
mapping of ATM or HDLC framed data. A flexible
parallel microprocessor interface is provided for
configuration and control. Industry standard UTOPIA II
and POS-PHY interface are also provided.
GENERAL FEATURES:
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On chip Clock and Data Recovery circuit for high
input jitter tolerance
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Meets E3/DS3 Jitter Tolerance Requirements
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Detects and Clears LOS as per G.775.
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Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation
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Compliant with jitter transfer template outlined in
ITU G.751, G.752, G.755 and GR-499-CORE,1995
standards
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Meets ETSI TBR 24 and GR-499 Jitter Transfer
Requirements
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On chip B3ZS/HDB3 encoder and decoder that can
be either enabled or disabled
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On-chip clock synthesizer provides the appropriate
rate clock from a single 12.288 MHz Clock
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Integrated T3/E3 Line Interface Unit
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Integrated Jitter Attenuator that can be selected
either in Receive or Transmit path
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On chip advanced crystal-less Jitter Attenuator
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Jitter Attenuator can be selected in Receive or
Transmit paths
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Flexible integrated Clock Multiplier that takes single
frequency clock and generates either DS3 or E3
frequency.
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16 or 32 bits selectable FIFO size
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Meets the Jitter and Wander specifications
described in T1.105.03b,ETSI TBR-24, Bellcore
GR-253 and GR-499 standards
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8/16 bit UTOPIA Level I and II and PPP Multi-PHY
Interface operating at 25, 33 or 50 MHz.
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HDLC Controller that provides the mapping/
extraction of either bit or byte mapped
encapsulated packet from DS3/E3 Frame.
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Jitter Attenuator can be disabled
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Typical power consumption 1.3W
DS3/E3 F
RAMER
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Contains on-chip 16 cell FIFO (configurable in
depths of 4, 8, 12 or 16 cells), in both the Transmit
(TxFIFO) and Receive Directions (RxFIFO)
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DS3 framer supports both M13 and C-bit parity.
鈥?/div>
DS3 framer meets ANSI T1.107 and T1.404
standards.
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Contains on-chip 54 byte Transmit and Receive
OAM Cell Buffer for transmission, reception and
processing of OAM Cells
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Detects OOF,LOF,AIS,RDI/FERF alarms.
鈥?/div>
Generation and Insertion of FEBE on received
parity errors supported.
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Supports ATM cell or PPP Packet Mapping
鈥?/div>
Supports M13 and C-Bit Parity Framing Formats
鈥?/div>
Supports DS3/E3 Clear-Channel Framing.
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Includes PRBS Generator and Receiver
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Supports Line, Cell, and PLCP Loop-backs
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Interfaces to 8 Bit wide Intel, Motorola, PowerPC,
and Mips 碌Ps
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Automatic insertion of RDI/FERF on alarm status.
鈥?/div>
E3 framer meets G.832,G.751 standards.
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Framers can be bypassed.
ATM/PPP PROTOCOL PROCESSOR
T
RANSMIT
C
ELL
P
ROCESSING
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Low power 3.3V, 5V Input Tolerant, CMOS
鈥?/div>
Available in 208 STBl PBGA Package
鈥?/div>
Extracts ATM cells
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Supports ATM cell payload scrambling
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Maps ATM cells into E3 or DS3 frame
鈥?/div>
PLCP frame and mapping of ATM cell streams
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
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(510) 668-7000
鈥?/div>
FAX (510) 668-7017
鈥?/div>
www.exar.com

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