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XRT75VL00D Datasheet

  • XRT75VL00D

  • E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

  • 92頁

  • EXAR   EXAR

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XRT75VL00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
FEBRUARY 2004
REV. 1.0.3
GENERAL DESCRIPTION
The XRT75VL00D is a single-channel fully integrated
Line Interface Unit (LIU) with Sonet Desynchronizer
for E3/DS3/STS-1 applications. It incorporates an
independent Receiver, Transmitter and Jitter
Attenuator in a single 52 pin TQFP package.
The XRT75VL00D can be configured to operate in
either E3 (34.368 MHz), DS3 (44.736 MHz) or STS-1
(51.84 MHz) modes. The transmitter can be turned
off (tri-stated) for redundancy support and for
conserving power.
The XRT75VL00D鈥檚 differential receiver provides high
noise interference margin and is able to receive the
data over 1000 feet of cable or with up to 12 dB of
cable attenuation.
The XRT75VL00D incorporates an advanced crystal-
less jitter attenuator that can be selected either in the
transmit or receive path. The jitter attenuator
performance meets the ETSI TBR-24 and Bellcore
GR-499 specifications. Also, the jitter attenuator can
be used for clock smoothing in SONET STS-1 to DS3
de-mapping.
The
XRT75VL00D
provides
both
Serial
Microprocessor Interface as well as Hardware mode
for programming and control.
The XRT75VL00D supports local, remote and digital
loop-backs. The XRT75VL00D also contains an on-
board Pseudo Random Binary Sequence (PRBS)
generator and detector with the ability to insert and
detect single bit error.
鈥?/div>
On-chip clock synthesizer provides the appropriate
rate clock from a single 12.288 MHz Clock.
鈥?/div>
Provides low jitter output clock.
TRANSMITTER:
鈥?/div>
Compliant with Bellcore GR-499, GR-253 and ANSI
T1.102 Specification for transmit pulse
鈥?/div>
Tri-state Transmit output capability for redundancy
applications
鈥?/div>
Transmitter can be turned on or off.
JITTER ATTENUATOR:
鈥?/div>
On chip advanced crystal-less Jitter Attenuator.
鈥?/div>
Jitter Attenuator can be selected in Receive or
Transmit paths.
鈥?/div>
16, 32 or 128 bits selectable FIFO size.
鈥?/div>
Meets the Jitter and Wander specifications
described in T1.105.03b,ETSI TBR-24, Bellcore
GR-253 and GR-499 standards.
鈥?/div>
Jitter Attenuator can be disabled.
鈥?/div>
De-Synchronizer for SONET STS-1 to DS-3
demapping.
CONTROL AND DIAGNOSTICS:
鈥?/div>
5 wire Serial Microprocessor Interface for control
and configuration.
鈥?/div>
Supports
Monitoring.
optional
internal
Transmit
Driver
FEATURES
RECEIVER:
鈥?/div>
On chip Clock and Data Recovery circuit for high
input jitter tolerance.
鈥?/div>
Meets
E3/DS3/STS-1
Requirements.
Jitter
Tolerance
鈥?/div>
Detects and Clears LOS as per G.775.
鈥?/div>
Meets Bellcore GR-499 CORE Jitter Transfer
Requirements.
鈥?/div>
PRBS error counter register to accumulate errors.
鈥?/div>
Hardware Mode for control and configuration.
鈥?/div>
Supports Local, Remote and Digital Loop-backs.
鈥?/div>
Single 3.3 V 鹵 5% power supply.
鈥?/div>
5 V Tolerant I/O.
鈥?/div>
Available in 52 pin TQFP.
鈥?/div>
-40擄C to 85擄C Industrial Temperature Range.
APPLICATIONS
鈥?/div>
E3/DS3 Access Equipment.
鈥?/div>
DSLAMs.
鈥?/div>
Digital Cross Connect Systems.
鈥?/div>
CSU/DSU Equipment.
鈥?/div>
Routers.
鈥?/div>
Fiber Optic Terminals.
鈥?/div>
Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation.
鈥?/div>
Compliant with jitter transfer template outlined in
ITU G.751, G.752, G.755 and GR-499-CORE,1995
standards.
鈥?/div>
Meets ETSI TBR 24 Jitter Transfer Requirements.
鈥?/div>
On chip B3ZS/HDB3 encoder and decoder that can
be either enabled or disabled.
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
鈥?/div>
(510) 668-7000
鈥?/div>
FAX (510) 668-7017
鈥?/div>
www.exar.com

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