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XRT73L03IV Datasheet

  • XRT73L03IV

  • 3 CHANNEL E3/DS3/STS-1 LINE INTERFCE UNIT

  • 673.20KB

  • 62頁

  • EXAR   EXAR

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謾莽
AUGUST 2000
PRELIMINARY
XRT73L03
REV. P1.0.13
3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
GENERAL DESCRIPTION
The XRT73L03 is a 3-Channel, E3/DS3/STS-1 Line
Interface Unit designed for E3, DS3 or SONET STS-1
applications and consists of three independent line
transmitters and receivers integrated on a single chip.
Each channel of the XRT73L03 can be configured to
support the E3 (34.368 Mbps), DS3 (44.736 Mbps) or
the SONET STS-1 (51.84 Mbps) rates. Each channel
can be configured to operate in a mode/data rate that
is independent of the other channels.
In the transmit direction, each channel in the
XRT73L03 encodes input data to either B3ZS or
HDB3 format and converts the data into the appropri-
ate pulse shapes for transmission over coaxial cable
via a 1:1 transformer.
In the receive direction, the XRT73L03 can perform
Equalization on incoming signals, perform Clock Re-
covery, decode data from either B3ZS or HDB3 for-
mat, convert the receive data into TTL/CMOS format,
check for LOS or LOL conditions and detect and de-
clare the occurrence of Line Code Violations.
APPLICATIONS
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Digital Cross Connect Systems
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CSU/DSU Equipment
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Routers
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Fiber Optic Terminals
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Multiplexers
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ATM Switches
FEATURES
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Meets E3/DS3/STS-1 Jitter Tolerance Require-
ments
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Full Loop-Back Capability
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Transmit and Receive Power Down Modes
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Full Redundancy Support
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Contains a 4-Wire Microprocessor Serial Interface
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Uses Minimum External components
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Single +3.3V Power Supply
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5V tolerant I/O
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-40擄C to +85擄C Operating Temperature Range
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Available in a Thermally Enhanced 120 pin TQFP
package
F
IGURE
1. XRT73L03 B
LOCK
D
IAGRAM
E3_Ch(n)
STS-1/DS3_Ch(n)
Host/(HW)
RLOL(n)
EXClk(n)
RxOFF
RxClkINV
RTIP(n)
RRing(n)
REQEN(n)
AGC/
Equalizer
Peak
Detector
Slicer
Clock
Recovery
Data
Recovery
Invert
RxClk(n)
LOSTHR(n)
SDI
SDO
SClk
CS
REGR
Serial
Processor
Interface
LOS Detector
HDB3/
B3ZS
Decoder
RPOS(n)
RNEG(n)
LCV(n)
ENDECDIS
RLOS(n)
LLB(n)
RLB(n)
TAOS(n)
Loop MUX
TTIP(n)
Pulse
Shaping
TRing(n)
MTIP(n)
MRing(n)
DMO(n)
Tx
Control
HDB3/
B3ZS
Encoder
Transmit
Logic
Duty Cycle Adjust
TPData(n)
TNData(n)
TxClk(n)
TxLEV(n)
TxOFF(n)
Device
Monitor
Channel 1 - (n) = 1
Channel 2 - (n) = 2
Channel 3 - (n) = 3
Notes: 1. (n) = 1, 2 or 3 for respective Channels
2. Serial Processor Interface input pins are shared by the three Channels in HOST Mode and redefined in Hardware Mode.
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
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(510) 668-7000
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FAX (510) 668-7017
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www.exar.com

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