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XR16C2850IJ44 Datasheet

  • XR16C2850IJ44

  • 3.3V AND 5V DUART WITH 128-BYTE FIFO

  • 43頁

  • EXAR   EXAR

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謾莽
APRIL 2002
XR16C2850
3.3V AND 5V DUART WITH 128-BYTE FIFO
REV. 2.0.0
GENERAL DESCRIPTION
The XR16C2850
1
(2850) is an enhanced dual univer-
sal asynchronous receiver and transmitter (UART).
Enhanced features include 128 bytes of TX and RX
FIFOs, programmable TX and RX FIFO trigger level,
FIFO level counters, automatic (RTS/CTS) hardware
and (Xon/Xoff) software flow control, automatic RS-
485 half duplex direction control output and data rates
up to 6.25 Mbps at 5V and 8X sampling clock. On-
board status registers provide the user with opera-
tional status and data error flags. An internal loop-
back capability allows system diagnostics. The 2850
has a full modem interface and can operate at 3.3 V
or 5 V and is pin-to-pin compatible to Exar鈥檚
ST16C2550 and XR16C2750 except the 48-TQFP
package. The 2850 register set is compatible to the
industry standard ST16C2550 and is available in 48-
pin TQFP 44-pin PLCC and 40-pin PDIP packages.
,
The 40-pin package does not offer TXRDY# and
RXRDY# pins (DMA signal monitoring) otherwise the
three package versions are the same.
N
OTE
:
1 Covered by U.S. Patent #5,649,122 and #5,832,205
FEATURES
鈥?/div>
Pin-to-pin compatible and functionally compatible to
Exar鈥檚 ST16C2550 and XR16L2750 and TI鈥檚
TL16C752B on the 44-PLCC package
鈥?/div>
Pin-alike Exar鈥檚 XR16L2750 and ST16C2550 48-
TQFP package but with additional CLK8/16, CLK-
SEL and HDCNTL inputs
鈥?/div>
Two independent UART channels
鈥?/div>
Register set compatible to 16C550
鈥?/div>
Up to 6.25 Mbps at 5V, and 4 Mbps at 3.3V
鈥?/div>
Transmit and Receive FIFOs of 128 bytes
鈥?/div>
Programmable TX and RX FIFO Trigger Levels
鈥?/div>
Transmit and Receive FIFO Level Counters
鈥?/div>
Automatic Hardware (RTS/CTS) Flow Control
鈥?/div>
Selectable Auto RTS Flow Control Hysteresis
鈥?/div>
Automatic Software (Xon/Xoff) Flow Control
鈥?/div>
Automatic RS-485 Half-duplex Direction Control
Output
鈥?/div>
Wireless Infrared (IrDA 1.0) Encoder/Decoder
鈥?/div>
Automatic sleep mode
鈥?/div>
Full modem interface
鈥?/div>
Device Identification and Revision
鈥?/div>
Crystal oscillator or external clock input
鈥?/div>
Industrial and commercial temperature ranges
鈥?/div>
48-TQFP and 44-PLCC packages
APPLICATIONS
鈥?/div>
Portable Appliances
鈥?/div>
Telecommunication Network Routers
鈥?/div>
Ethernet Network Routers
鈥?/div>
Cellular Data Devices
鈥?/div>
Factory Automation and Process Controls
F
IGURE
1. XR16C2850 B
LOCK
D
IAGRAM
A2:A0
D7:D0
IOR#
IOW#
CSA#
CSB#
INTA
INTB
TXRDYA#
TXRDYB#
RXRDYA#
RXRDYB#
HDCNTL#
CLKSEL
CLK8/16
Reset
8-bit Data
Bus
Interface
UART Channel A
UART
Regs
BRG
128 Byte TX FIFO
TX & RX
IR
ENDEC
3.3V or 5V VCC
GND
TXA, RXA, DTRA#,
DSRA#, RTSA#,
DTSA#, CDA#, RIA#,
OP2A#
128 Byte RX FIFO
TXB, RXB, DTRB#,
DSRB#, RTSB#,
CTSB#, CDB#, RIB#,
OP2B#
XTAL1
XTAL2
UART Channel B
(same as Channel A)
Crystal Osc/Buffer
EXAR
Corporation 48720 Kato Road, Fremont CA, 94538
鈥?/div>
(510) 668-7000
鈥?/div>
FAX (510) 668-7017
鈥?/div>
www.exar.com
鈥?/div>
uarttechsupport@exar.com

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