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XQVR600-4CB228M Datasheet

  • XQVR600-4CB228M

  • QPro Virtex 2.5V Radiation Hardened FPGAs

  • 14頁

  • XILINX   XILINX

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0
R
QPro Virtex 2.5V Radiation
Hardened FPGAs
0
2
DS028 (v1.2) November 5, 2001
Preliminary Product Specification
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Complete support for Unified Libraries, Relationally
Placed Macros, and Design Manager
Wide selection of PC and workstation platforms
Unlimited reprogrammability
Four programming modes
Features
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
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0.22
碌m
5-layer epitaxial process
QML certified
Radiation hardened FPGAs for space and satellite
applications
Guaranteed total ionizing dose to 100K Rad(si)
Latch-up immune to LET = 125 MeV cm
2
/mg
SEU immunity achievable with recommended
redundancy implementation
Guaranteed over the full military temperature range
(鈥?5擄C to +125擄C)
Fast, high-density Field-Programmable Gate Arrays
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Densities from 100k to 1M system gates
System performance up to 200 MHz
Hot-swappable for Compact PCI
16 high-performance interface standards
Connects directly to ZBTRAM devices
Four dedicated delay-locked loops (DLLs) for
advanced clock control
Four primary low-skew global clock distribution
nets, plus 24 secondary global nets
LUTs configurable as 16-bit RAM, 32-bit RAM,
16-bit dual-ported RAM, or 16-bit Shift Register
Configurable synchronous dual-ported 4k-bit
RAMs
Fast interfaces to external high-performance RAMs
Dedicated carry logic for high-speed arithmetic
Dedicated multiplier support
Cascade chain for wide-input functions
Abundant registers/latches with clock enable, and
dual synchronous/asynchronous set and reset
Internal 3-state bussing
IEEE 1149.1 boundary-scan logic
Die-temperature sensing device
SRAM-based in-system configuration
Available to Standard Microcircuit Drawings. Contact
Defense Supply Center Columbus (DSCC) for more
information at http://www.dscc.dla.mil
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5962-99572 for XQVR300
5962-99573 for XQVR600
5962-99574 for XQVR1000
Description
The QPro鈩?Virtex鈩?FPGA family delivers high-perfor-
mance, high-capacity programmable logic solutions. Dra-
matic increases in silicon efficiency result from optimizing
the new architecture for place-and-route efficiency and
exploiting an aggressive 5-layer-metal 0.22
碌m
CMOS pro-
cess. These advances make QPro Virtex FPGAs powerful
and flexible alternatives to mask-programmed gate arrays.
The Virtex radiation hardened family comprises the three
members shown in
Table 1.
Building on experience gained from previous generations of
FPGAs, the Virtex family represents a revolutionary step
forward in programmable logic design. Combining a wide
variety of programmable system features, a rich hierarchy of
fast, flexible interconnect resources, and advanced process
technology, the QPro Virtex family delivers a high-speed
and high-capacity programmable logic solution that
enhances design flexibility while reducing time-to-market.
Refer to the
鈥淰irtex鈩?2.5V Field Programmable Gate
Arrays鈥?/span>
commercial data sheet for more information on
device architecture and timing specifications.
Multi-standard SelectI/O鈩?interfaces
Built-in clock-management circuitry
Hierarchical memory system
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Flexible architecture that balances speed and density
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Supported by FPGA Foundation鈩?and Alliance
Development Systems
漏 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS028 (v1.2) November 5, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
1

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