4 Megabit Puma Module
XM28C040P
512K x 8 Bit
High Density 5 Volt Byte Alterable Nonvolatile Memory Array
FEATURES
鈥?High Density Memory Module
鈥?50ns, 200ns, and 250ns Access Times
Available
鈥? Megabit Memory in 1 square inch.
鈥?Flexible Multiplane Architecture
鈥擣our Separate Chip Selects
鈥?2 Separate I/Os
鈥?User Con鏗乬urable I/Os鈥攛8, x16, or x32
鈥?User Con鏗乬urable Page Size鈥?4 Double-
words, 128 Words, or 256 Bytes
鈥擟oncurrent Read/Write Operations
鈥?Able to Continue Reading During a
Nonvolatile Write Cycle.
鈥?5 Volt Byte or Page Alterable
鈥擭o Erase Before Write
鈥?Software Data Protection
鈥?Early End of Write Polling
鈥擠ATA Polling
鈥擳oggle Bit Polling
鈥?High Reliability
鈥擡ndurance: 100,000 Cycles
鈥擠ata Retention: 100 Years
FUNCTIONAL DIAGRAM
OE WE1 CE1
WE2 CE2
WE3 CE3
WE4 CE4
DESCRIPTION
The XM28C040P is a high density CMOS byte alter-
able nonvolatile memory array constructed on a co-
鏗乺ed ceramic substrate using Xicor鈥檚 128K x 8 compo-
nents in 32-pad leadless chip carriers. The Substrate is
a 66-pin ceramic pin grid array.
The module is con鏗乬ured with four separate chip
enable and write enable inputs and 32 separate I/Os.
This, along with the small footprint, provides the end
user with a large degree of 鏗俥xibility in board layout and
memory con鏗乬uration. In addition, with the large num-
ber of pins and the growth path being implemented, the
module will be able to grow to 16 megabits.
128K x 8
128K x 8
128K x 8
128K x 8
A0-A16 I/O0-I/O7
I/O8-I/O15
I/O16-I/O23
I/O24-I/O31
漏
Xicor, 1995, 1996 Patents Pending
7053 8/13/97 T0/C0/D0 SH
1
Characteristics subject to change without notice
XICOR
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