1 Megabit Puma Module
XM28C010P
鈥?High Reliability
鈥擡ndurance: 100,000 Cycles
鈥擠ata Retention: 100 Years
DESCRIPTION
32K x 32 Bit
High Speed 5 Volt Byte Alterable Nonvolatile Memory Array
FEATURES
鈥?High Speed, High Density Memory Module
鈥?50ns, 120ns, 90ns and 70ns Access Times
Available
鈥? Megabit Memory in 1 square inch.
鈥?Flexible Multiplane Architecture
鈥擣our Separate Chip Selects
鈥?2 Separate I/Os
鈥?User Con鏗乬urable I/Os鈥攛8, x16, or x32
鈥?User Con鏗乬urable Page Size鈥?4 Double-
words, 128 Words, or 256 Bytes
鈥擟oncurrent Read/Write Operations
鈥?Able to Continue Reading During a
Nonvolatile Write Cycle.
鈥?5 Volt Byte or Page Alterable
鈥擭o Erase Before Write
鈥?Software Data Protection
鈥?Early End of Write Polling
鈥擠ATA Polling
鈥擳oggle Bit Polling
The XM28C010P is a high speed, high density CMOS
byte alterable nonvolatile memory array constructed on
a co-鏗乺ed ceramic substrate using Xicor鈥檚 High Speed
32K x 8 components in 32-pad leadless chip carriers.
The Substrate is a 66-pin ceramic pin grid array.
The module is con鏗乬ured with four separate chip
enable and write enable inputs and 32 separate I/Os.
This, along with the small footprint, provides the end
user with a large degree of 鏗俥xibility in board layout and
memory con鏗乬uration. In addition, with the large num-
ber of pins and the growth path being implemented, the
module will be able to grow to 16 megabits.
FUNCTIONAL DIAGRAM
OE
WE1
CE1
WE2
CE2
WE3
CE3
WE4
CE4
32k x 8
32k x 8
32k x 8
32k x 8
A0鈥揂15
I/O0鈥揑/O7
I/O8鈥揑/O15
I/O16鈥揑/O23
I/O24鈥揑/O31
6491 ILL F01
漏
Xicor, 1995, 1996 Patents Pending
6491-1.3 8/12/97 T0/C2/D0 NS
1
Characteristics subject to change without notice
XICOR
1
2
3
