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XCV100-6PQ240I Datasheet

  • XCV100-6PQ240I

  • Field Programmable Gate Arrays

  • 4頁

  • XILINX   XILINX

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0
R
Virtex鈩?2.5 V
Field Programmable Gate Arrays
0
3
DS003-1 (v2.5 ) April 2, 2001
Product Specification
Features
鈥?/div>
Fast, high-density Field-Programmable Gate Arrays
- Densities from 50k to 1M system gates
- System performance up to 200 MHz
- 66-MHz PCI Compliant
- Hot-swappable for Compact PCI
Multi-standard SelectIO鈩?interfaces
- 16 high-performance interface standards
- Connects directly to ZBTRAM devices
Built-in clock-management circuitry
- Four dedicated delay-locked loops (DLLs) for
advanced clock control
- Four primary low-skew global clock distribution
nets, plus 24 secondary local clock nets
Hierarchical memory system
- LUTs configurable as 16-bit RAM, 32-bit RAM,
16-bit dual-ported RAM, or 16-bit Shift Register
- Configurable synchronous dual-ported 4k-bit
RAMs
- Fast interfaces to external high-performance RAMs
Flexible architecture that balances speed and density
- Dedicated carry logic for high-speed arithmetic
- Dedicated multiplier support
- Cascade chain for wide-input functions
- Abundant registers/latches with clock enable, and
dual synchronous/asynchronous set and reset
- Internal 3-state bussing
- IEEE 1149.1 boundary-scan logic
- Die-temperature sensor diode
鈥?/div>
Supported by FPGA Foundation鈩?and Alliance
Development Systems
- Complete support for Unified Libraries, Relationally
Placed Macros, and Design Manager
- Wide selection of PC and workstation platforms
SRAM-based in-system configuration
- Unlimited re-programmability
- Four programming modes
0.22
m
m 5-layer metal process
100% factory tested
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Description
The Virtex FPGA family delivers high-performance,
high-capacity programmable logic solutions. Dramatic
increases in silicon efficiency result from optimizing the new
architecture for place-and-route efficiency and exploiting an
aggressive 5-layer-metal 0.22
m
m CMOS process. These
advances make Virtex FPGAs powerful and flexible alterna-
tives to mask-programmed gate arrays. The Virtex family
comprises the nine members shown in
Table 1.
Building on experience gained from previous generations of
FPGAs, the Virtex family represents a revolutionary step
forward in programmable logic design. Combining a wide
variety of programmable system features, a rich hierarchy of
fast, flexible interconnect resources, and advanced process
technology, the Virtex family delivers a high-speed and
high-capacity programmable logic solution that enhances
design flexibility while reducing time-to-market.
鈥?/div>
鈥?/div>
Table 1:
Virtex Field-Programmable Gate Array Family Members
Device
XCV50
XCV100
XCV150
XCV200
XCV300
XCV400
XCV600
XCV800
XCV1000
System Gates
57,906
108,904
164,674
236,666
322,970
468,252
661,111
888,439
1,124,022
CLB Array
16x24
20x30
24x36
28x42
32x48
40x60
48x72
56x84
64x96
Logic Cells
1,728
2,700
3,888
5,292
6,912
10,800
15,552
21,168
27,648
Maximum
Available I/O
180
180
260
284
316
404
512
512
512
Block RAM
Bits
32,768
40,960
49,152
57,344
65,536
81,920
98,304
114,688
131,072
Maximum
SelectRAM+鈩?Bits
24,576
38,400
55,296
75,264
98,304
153,600
221,184
301,056
393,216
漏 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS003-1 (v2.5 ) April 2, 2001
Product Specification
www.xilinx.com
1-800-255-7778
Module 1 of 4
1

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