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XCR3256XL-10PQ144I Datasheet

  • XCR3256XL-10PQ144I

  • 256 Macrocell CPLD

  • 239.81KB

  • 10頁

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XCR3256XL 256 Macrocell CPLD
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DS013 (v1.2) May 3, 2000
Preliminary Product Specification
Features
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7.5 ns pin-to-pin logic delays
System frequencies up to 140 MHz
256 macrocells with 6,000 usable gates
Available in small footprint packages
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144-pin TQFP (116 user I/O pins)
208-pin PQFP (160 user I/O)
280-ball CS BGA (160 user I/O)
Ultra low power operation
5V tolerant I/O pins with 3.3V core supply
Advanced 0.35 micron five metal layer re-
programmable process
FZP鈩?CMOS design technology
In-system programming
Input registers
Predictable timing model
Up to 23 clocks available per logic block
Excellent pin retention during design changes
Full IEEE Standard 1149.1 boundary-scan (JTAG)
Four global clocks
Eight product term control terms per logic block
Description
The XCR3256XL is a 3.3V, 256 macrocell CPLD targeted at
power sensitive designs that require leading edge program-
mable logic solutions. A total of 16 logic blocks provide
6,000 usable gates. Pin-to-pin propagation delays are
7.5 ns with a maximum system frequency of 140 MHz.
TotalCMOS鈩?Design Technique for
Fast Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technol-
ogy and design technique. Xilinx employs a cascade of
CMOS gates to implement its sum of products instead of
the traditional sense amp approach. This CMOS gate
implementation allows Xilinx to offer CPLDs that are both
high performance and low power, breaking the paradigm
that to have low power, you must have low performance.
Refer to
Figure 1
and
Table 1
showing the I
CC
vs. Fre-
quency of our XCR3256XL TotalCMOS CPLD (data taken
with 16 up/down, loadable 16-bit counters at 3.3V, 25
擄
C).
Optimized for 3.3V systems
Advanced system features
Fast ISP programming times
Port Enable pin for additional I/O
2.7V to 3.6V industrial grade voltage range
Programmable slew rate control per output
Security bit prevents unauthorized access
Refer to XPLA3 family data sheet (DS012) for
architecture description
漏 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners.
All specifications are subject to change without notice.
DS013 (v1.2) May 3, 2000
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
1

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