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XCCACEM16SERIES Datasheet

  • XCCACEM16SERIES

  • System ACE MPM Solution

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System ACE MPM Solution
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DS087 (v1.0) September 25, 2001
Advance Product Specification
Summary of Features
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System level, high capacity, pre-configured solution for
Virtex and Spartan FPGAs
Industry standard Flash memory die combined with
Xilinx controller technology in a single package
Effortless density migration:
- XCCACEM16-BG388I (16 Megabit (Mb))
- XCCACEM32-BG388I (32 Mb)
- XCCACEM64-BG388I (64 Mb)
All densities are available in the 388-pin Ball Grid Array
package
VCC I/O: 1.8V, 2.5V, and 3.3V
Configuration rates up to 152 Mb per second (Mb/s)
Flexible configuration solution:
- SelectMAP (control up to four FPGAs)
- Slave-Serial
- Concurrent Slave-Serial (up to eight separate
chains)
Patented compression technology (up to
2x compression)
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JTAG interface allows:
- Access to the standard Flash memory
- Boundary Scan testing
Native interface to the standard Flash memory is
provided for:
- External parallel programming
- Processor access to unused Flash memory
locations
Supports up to eight separate design sets (selectable
by mode pins or via JTAG), enabling systems to
reconfigure FPGAs for different functions
Compatible with IEEE Standard 1532
User-friendly software to format and program the
bitstreams into the standard Flash via the patented
Flash programming engine
Internet Reconfigurable Logic (IRL) upgradable system
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Description
The System ACE鈩?Multi-Package Module (MPM) solution
addresses the need for a space-efficient, pre-engineered,
high-density configuration solution in multiple FPGA sys-
tems. The System ACE technology is a ground-breaking
in-system programmable configuration solution that pro-
vides substantial savings in development effort and cost per
bit over traditional PROM and embedded solutions for high
capacity FPGA systems. As shown in
Figure 1,
the System
ACE MPM solution is a multi-package module that includes
the System ACE MPM controller, a configuration PROM,
and an AMD Flash Memory.
The System ACE MPM has four major interfaces. (See
Figure 2.)
The boundary scan JTAG interface is provided for
boundary scan test and boundary-scan-based Flash mem-
ory programming. The system control interface provides an
input for the system clock, design set selection pins, system
configuration control signals, and system configuration sta-
tus signals.
The native Flash memory interface provides direct read and
write access to the Flash memory unit. The target FPGA
interface provides the signals to configure target FPGAs via
the Slave-Serial, concurrent Slave-Serial, or SelectMAP
configuration modes.
Separate power pins provide voltage compatibility control
for the target FPGA configuration interface and for the sys-
tem control/status interface.
See
Figure 3
for a complete view of the components and
schematic of the signals in the System ACE MPM.
漏 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS087 (v1.0) September 25, 2001
Advance Product Specification
www.xilinx.com
1-800-255-7778
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