鈥?/div>
5 ns pin-to-pin logic delays
System frequency up to 178 MHz
72 macrocells with 1,600 usable gates
Available in small footprint packages
- 44-pin PLCC (34 user I/O pins)
- 44-pin VQFP (34 user I/O pins)
- 48-pin CSP (38 user I/O pins)
- 64-pin VQFP (52 user I/O pins)
- 100-pin TQFP (72 user I/O pins)
Optimized for high-performance 3.3V systems
- Low power operation
- 5V tolerant I/O pins accept 5 V, 3.3V, and 2.5V
signals
- 3.3V or 2.5V output capability
- Advanced 0.35 micron feature size CMOS
FastFLASH鈩?technology
Advanced system features
- In-system programmable
- Superior pin-locking and routability with
FastCONNECT II鈩?switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with
individual product-term allocation
- Local clock inversion with three global and one
product-term clocks
- Individual output enable per output pin
- Input hysteresis on all user and boundary-scan pin
inputs
- Bus-hold circuitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
- Endurance exceeding 10,000 program/erase
cycles
- 20 year data retention
- ESD protection exceeding 2,000V
Pin-compatible with 5V-core XC9572 device in the
44-pin PLCC package and the 100-pin TQFP package
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XL device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
For a general estimate of I
CC
, the following equation may be
used:
I
CC
(mA) = MC
HP
(0.5) + MC
LP
(0.3) + MC(0.0045 mA/MHz) f
Where:
MC
HP
= Macrocells in high-performance (default) mode
MC
LP
= Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
This calculation is based on typical operating conditions
using a pattern of 16-bit up/down counters in each Function
Block with no output loading. The actual I
CC
value varies
with the design application and should be verified during
normal system operation.
Figure 1
shows the above estimation in a graphical form.
100
178 MHz
鈥?/div>
鈥?/div>
Typical ICC (mA)
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
80
60
Hi
g
e
hP
rf
r
a
orm
nc
e
104 MHz
40
Lo
w
Po
we
鈥?/div>
20
Description
The XC9572XL is a 3.3V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
0
100
50
150
Clock Frequency (MHz)
200
DS057_01_081500
Figure 1:
Typical I
CC
vs. Frequency for XC9572XL
漏 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS057 (v1.1) August 28, 2000
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
1
XC9572XL-10VQ64I 產(chǎn)品屬性
160
集成電路 (IC)
嵌入式 - CPLD（復(fù)雜可編程邏輯器件）
XC9500XL
系統(tǒng)內(nèi)可編程（最少 10,000 次編程/擦除循環(huán)）
10.0ns
3 V ~ 3.6 V
4
72
1600
52
-40°C ~ 85°C
表面貼裝
64-TQFP
64-VQFP（10x10）
托盤
122-1512-ND - KIT DESIGN CPLD W/BATT HOLDER
XC9572XL-10VQ64I相關(guān)型號PDF文件下載
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描述
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