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High-performance
- 5 ns pin-to-pin logic delays on all pins
- f
CNT
to 125 MHz
Large density range
- 36 to 288 macrocells with 800 to 6,400 usable gates
5 V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
Enhanced pin-locking architecture
Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables, set
and reset signals
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design protection
High-drive 24 mA outputs
3.3 V or 5 V I/O capability
Advanced CMOS 5V FastFLASH technology
Supports parallel programming of multiple XC9500
devices
Family Overview
The XC9500 CPLD family provides advanced in-system
programming and test capabilities for high performance,
general purpose logic integration. All devices are in-system
programmable for a minimum of 10,000 program/erase
cycles. Extensive IEEE 1149.1 (JTAG) boundary-scan sup-
port is also included on all family members.
As shown in
Table 1,
logic density of the XC9500 devices
ranges from 800 to over 6,400 usable gates with 36 to 288
registers, respectively. Multiple package options and asso-
ciated I/O capacity are shown in
Table 2.
The XC9500 fam-
ily is fully pin-compatible allowing easy design migration
across multiple density options in a given package foot-
print.
The XC9500 architectural features address the require-
ments of in-system programmability. Enhanced pin-locking
capability avoids costly board rework. An expanded JTAG
instruction set allows version control of programming pat-
terns and in-system debugging. In-system programming
throughout the full device operating range and a minimum
of 10,000 program/erase cycles provide worry-free recon-
figurations and system field upgrades.
Advanced system features include output slew rate control
and user-programmable ground pins to help reduce system
noise. I/Os may be configured for 3.3 V or 5 V operation. All
outputs provide 24 mA drive.
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Architecture Description
Each XC9500 device is a subsystem consisting of multiple
Function Blocks (FBs) and I/O Blocks (IOBs) fully intercon-
nected by the FastCONNECT switch matrix. The IOB pro-
vides buffering for device inputs and outputs. Each FB
provides programmable logic capability with 36 inputs and
18 outputs. The FastCONNECT switch matrix connects all
FB outputs and input signals to the FB inputs. For each FB,
12 to 18 outputs (depending on package pin-count) and
associated output enable signals drive directly to the IOBs.
See
Figure 1.
September 15, 1999 (Version 5.0)
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