鈥?/div>
7.5 ns pin-to-pin logic delays on all pins
f
CNT
to 111 MHz
144 macrocells with 3,200 usable gates
Up to 133 user I/O pins
5 V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
Enhanced pin-locking architecture
Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables, set
and reset signals
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design protection
High-drive 24 mA outputs
3.3 V or 5 V I/O capability
Advanced CMOS 5V FastFLASH technology
Supports parallel programming of more than one
XC9500 concurrently
Available in 100-pin PQFP, 100-pin TQFP, and 160-pin
PQFP packages
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
600
(480)
Typical I
CC
(mA)
400
H
erf
igh P
orma
nce
(320)
(300)
200
(160)
er
Pow
Low
0
Description
The XC95144 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of eight
36V18 Function Blocks, providing 3,200 usable gates with
propagation delays of 7.5 ns. See
Figure 2
for the architec-
ture overview.
50
Clock Frequency (MHz)
100
X5898B
Figure 1: Typical I
cc
vs. Frequency for XC95144
Power Management
Power dissipation can be reduced in the XC95144 by con-
figuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
December 4, 1998 (Version 4.0)
1
XC95144-7PQ160C 產(chǎn)品屬性
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