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XC73144
144-Macrocell CMOS EPLD
Product Speci鏗乧ations
Features
鈥?High-Performance EPLD
鈥?7.5 ns pin-to-pin speed on all fast inputs
鈥?100 MHz maximum clock frequency
鈥?Advanced Dual-Block architecture
鈥?Four Fast Function Blocks
鈥?Twelve High-Density Function Blocks
鈥?100% interconnect matrix
鈥?High-Speed arithmetic carry network
鈥?1 ns ripple-carry delay per bit
鈥?43 MHz 16-bit accumulators
鈥?144 Macrocells with programmable I/O architecture
鈥?Up to 132 inputs programmable as direct, latched, or
registered
鈥?All outputs with 24 mA drive
鈥?3.3 V or 5 V I/O operation
鈥?Meets JEDEC Standard (8-1A) for 3.3 V
鹵
0.3 V
鈥?Power management options
鈥?Multiple security bits for design protection
鈥?160-pin plastic quad flat pack and 225-pin ball-grid-
array packages
鈥?100% PCI compliant
鈥?Programmable slew rate
鈥?Programmable ground control
The Universal Interconnect Matrix connects the Function
Blocks to each other and to all input pins, providing 100%
connectivity between the Function Blocks. This allows
logic functions to be mapped into the Function Blocks and
interconnected without routing restrictions.
The XC73144 is designed in a 0.8
碌
CMOS EPROM tech-
nology.
In addition, the XC73144 includes a programmable power
management feature to specify high-performance or low-
power operation on an individual Macrocell-by-Macrocell
basis. Unused Macrocells are automatically turned off to
minimize power dissipation. Designers can operate
speed-critical paths at maximum performance, while non-
critical paths dissipate less power.
Xilinx development software (XEPLD) supports all mem-
bers of XC7300 family. The designer can create, imple-
ment, and verify digital logic circuits for EPLD devices
using the Xilinx XEPLD Development System. Designs
can be represented as schematics consisting of XEPLD
library components, as behavioral descriptions, or as a
mixture of both. The XEPLD translator automatically per-
forms logic optimization, collapsing, mapping and routing
without user intervention. After compiling the design,
XEPLD translator produces documentation for design
analysis and creates a programming 鏗乴e to con鏗乬ure the
device.
The following lists some of the XEPLD Development Sys-
tem features.
鈥?Familiar design approach similar to TTL and PLD
techniques
鈥?Converts netlist to fuse map in minutes using a 386/
486 PC or workstation platform
鈥?Interfaces to standard third-party CAE schematics,
simulation tools, and behavioral languages
鈥?Timing simulation using Viewsim, OrCAD VST, Mentor,
LMC and other tools compatible with the Xilinx Netlist
Format (XNF)
General Description
The XC73144 is a member of the Xilinx Dual-Block EPLD
family. It consists of four Fast Function Blocks and twelve
High-Density Function Blocks interconnected by a central
Universal Interconnect Matrix (UIM).
The sixteen Function Blocks in the XC73144 are PAL-like
structures, complete with programmable product term
arrays and programmable multilevel Macrocells. Each
Function Block receives 24 inputs, contains nine Macro-
cells con鏗乬urable for registered or combinatorial logic and
produces nine outputs which feedback to the UIM and
output pins.
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