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Industry First Platform FPGA Solution
IP-Immersion鈩?Architecture
- Densities from 40K to 8M system gates
- 420 MHz internal clock speed (Advance Data)
- 840+ Mb/s I/O (Advance Data)
SelectRAM鈩?Memory Hierarchy
- 3 Mb of True Dual-Port鈩?RAM in 18-Kbit block
SelectRAM resources
- Up to 1.5 Mb of distributed SelectRAM resources
- High-performance interfaces to external memory
路
DDR-SDRAM interface
路
FCRAM interface
路
QDR鈩?SRAM interface
路
Sigma RAM interface
Arithmetic Functions
- Dedicated 18-bit x 18-bit multiplier blocks
- Fast look-ahead carry logic chains
Flexible Logic Resources
- Up to 93,184 internal registers / latches with Clock
Enable
- Up to 93,184 look-up tables (LUTs) or cascadable
16-bit shift registers
- Wide multiplexers and wide-input function support
- Horizontal cascade chain and Sum-of-Products
support
- Internal 3-state bussing
High-Performance Clock Management Circuitry
- Up to 12 DCM (Digital Clock Manager) modules
路
Precise clock de-skew
路
Flexible frequency synthesis
路
High-resolution phase shifting
- 16 global clock multiplexer buffers
Active Interconnect鈩?Technology
- Fourth generation segmented routing structure
- Predictable, fast routing delay, independent of
fanout
SelectI/O-Ultra鈩?Technology
- Up to 1,108 user I/Os
- 19 single-ended standards and six differential
standards
- Programmable sink current (2 mA to 24 mA) per I/O
Digitally Controlled Impedance (DCI) I/O: on-chip
termination resistors for single-ended I/O standards
- PCI-X @ 133 MHz, PCI @ 66 MHz and 33 MHz
compliance, and CardBus compliant
- Differential Signaling
路
840 Mb/s Low-Voltage Differential Signaling I/O
(LVDS) with current mode drivers
路
Bus LVDS I/O
路
Lightning Data Transport (LDT) I/O with current
driver buffers
路
Low-Voltage Positive Emitter-Coupled Logic
(LVPECL) I/O
路
Built-in DDR Input and Output registers
- Proprietary high-performance SelectLink鈩?/div>
Technology
路
High-bandwidth data path
路
Double Data Rate (DDR) link
路
Web-based HDL generation methodology
Supported by Xilinx Foundation鈩?and Alliance鈩?/div>
Series Development Systems
- Integrated VHDL and Verilog design flows
- Compilation of 10M system gates designs
- Internet Team Design (ITD) tool
SRAM-Based In-System Configuration
- Fast SelectMAP鈩?configuration
- Triple Data Encryption Standard (DES) security
option (Bitstream Encryption)
- IEEE1532 support
- Partial reconfiguration
- Unlimited re-programmability
- Readback capability
0.15 碌m 8-Layer Metal process with 0.12 碌m
high-speed transistors
1.5 V (V
CCINT
) core power supply, dedicated 3.3 V
V
CCAUX
auxiliary and V
CCO
I/O power supplies
IEEE 1149.1 compatible boundary-scan logic support
Flip-Chip and Wire-Bond Ball Grid Array (BGA)
packages in three standard fine pitches (0.80mm,
1.00mm, and 1.27mm)
100% factory tested
-
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漏 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS031-1 (v1.7) October 2, 2001
Advance Product Specification
www.xilinx.com
1-800-255-7778
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