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Industry First Platform FPGA Solution
IP-Immersion鈩?Architecture
- Densities from 40K to 8M system gates
- 420 MHz internal clock speed (Advance Data)
- 840+ Mb/s I/O (Advance Data)
SelectRAM鈩?Memory Hierarchy
- 3 Mb of True Dual-Port鈩?RAM in 18-Kbit block
SelectRAM resources
- Up to 1.5 Mb of distributed SelectRAM resources
- High-performance interfaces to external memory
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DDR-SDRAM interface
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FCRAM interface
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QDR鈩?SRAM interface
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Sigma RAM interface
Arithmetic Functions
- Dedicated 18-bit x 18-bit multiplier blocks
- Fast look-ahead carry logic chains
Flexible Logic Resources
- Up to 93,184 internal registers / latches with Clock
Enable
- Up to 93,184 look-up tables (LUTs) or cascadable
16-bit shift registers
- Wide multiplexers and wide-input function support
- Horizontal cascade chain and Sum-of-Products
support
- Internal 3-state bussing
High-Performance Clock Management Circuitry
- Up to 12 DCM (Digital Clock Manager) modules
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Precise clock de-skew
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Flexible frequency synthesis
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High-resolution phase shifting
- 16 global clock multiplexer buffers
Active Interconnect鈩?Technology
- Fourth generation segmented routing structure
- Predictable, fast routing delay, independent of
fanout
SelectI/O-Ultra鈩?Technology
- Up to 1,108 user I/Os
- 19 single-ended standards and six differential
standards
- Programmable sink current (2 mA to 24 mA) per I/O
Digitally Controlled Impedance (DCI) I/O: on-chip
termination resistors for single-ended I/O standards
- PCI-X @ 133 MHz, PCI @ 66 MHz and 33 MHz
compliance, and CardBus compliant
- Differential Signaling
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840 Mb/s Low-Voltage Differential Signaling I/O
(LVDS) with current mode drivers
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Bus LVDS I/O
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Lightning Data Transport (LDT) I/O with current
driver buffers
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Low-Voltage Positive Emitter-Coupled Logic
(LVPECL) I/O
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Built-in DDR Input and Output registers