鈥?/div>
System level features
- SelectRAM+鈩?hierarchical memory:
路
16 bits/LUT distributed RAM
路
Configurable 4K-bit true dual-port block RAM
路
Fast interfaces to external RAM
- Fully 3.3V PCI compliant to 64 bits at 66 MHz and
CardBus compliant
- Low-power segmented routing architecture
- Full readback ability for verification/observability
- Dedicated carry logic for high-speed arithmetic
- Efficient multiplier support
- Cascade chain for wide-input functions
- Abundant registers/latches with enable, set, reset
- Four dedicated DLLs for advanced clock control
- Four primary low-skew global clock distribution nets
- IEEE 1149.1 compatible boundary scan logic
Versatile I/O and packaging
- Low cost packages available in all densities
- Family footprint compatibility in common packages
- 19 high-performance interface standards, including
LVDS and LVPECL
- Up to 120 differential I/O pairs that can be input,
output, or bidirectional
- Zero hold time simplifies system timing
Fully supported by powerful Xilinx ISE development
system
- Fully automatic mapping, placement, and routing
- Integrated with design entry and verification tools
Introduction
The Spartan鈩?IIE 1.8V Field-Programmable Gate Array
family gives users high performance, abundant logic
resources, and a rich feature set, all at an exceptionally low
price. The five-member family offers densities ranging from
50,000 to 300,000 system gates, as shown in
Table 1.
Sys-
tem performance is supported beyond 200 MHz.
Spartan-IIE devices deliver more gates, I/Os, and features
per dollar than other FPGAs by combining advanced pro-
cess technology with a streamlined architecture based on
the proven Virtex鈩?E platform. Features include block RAM
(to 64K bits), distributed RAM (to 98,304 bits), 19 selectable
I/O standards, and four DLLs (Delay-Locked Loops). Fast,
predictable interconnect means that successive design iter-
ations continue to meet timing requirements.
The Spartan-IIE family is a superior alternative to
mask-programmed ASICs. The FPGA avoids the initial cost,
lengthy development cycles, and inherent risk of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary (impossible with ASICs).
鈥?/div>
Features
鈥?/div>
Second generation ASIC replacement technology
- Densities as high as 6,912 logic cells with up to
300,000 system gates
- Streamlined features based on Virtex-E
architecture
- Unlimited in-system reprogrammability
- Very low cost
鈥?/div>
Table 1:
Spartan-IIE FPGA Family Members
Logic
Cells
1,728
2,700
3,888
5,292
6,912
Typical
System Gate Range
(Logic and RAM)
23,000 - 50,000
37,000 - 100,000
52,000 - 150,000
71,000 - 200,000
93,000 - 300,000
CLB
Array
(R x C)
16 x 24
20 x 30
24 x 36
28 x 42
32 x 48
Total
CLBs
384
600
864
1,176
1,536
Maximum
Available
User I/O
182
202
263
289
329
Maximum
Differential
I/O Pairs
84
86
114
120
120
Distributed
RAM Bits
24,576
38,400
55,296
75,264
98,304
Block
RAM Bits
32K
40K
48K
56K
64K
Device
XC2S50E
XC2S100E
XC2S150E
XC2S200E
XC2S300E
漏 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS077-1 (v1.0) November 15, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
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