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Industries best 0.18 micron CMOS CPLD
- 4.0 ns pin-to-pin logic delays
- less than 100
碌A(chǔ)
standby current consumption
- 64 macrocells with up to 1,600 logic gates
- Fast input registers
- Slew rate control on individual outputs
- LVCMOS 1.8V through 3.3V
- LVTTL 3.3V
Available in multiple package styles
- 44-pin PLCC with 33 user I/O
- 44-pin VQFP with 33 user I/O
- 56-ball CP (0.05mm) BGA with 45 user I/O
- 100-pin VQFP with 64 user I/O
Optimized for high performance 1.8V systems
- Ultra low power operation
- Advanced 0.18 micron 4-metal layer Non-volatile
process
Advanced system features
- Quadruple enhanced security
- Multi-voltage system interface
- Hot pluggable
- IEEE1532 In-system programmable
- Superior pin locking through PLA array
- Input hysteresis (Schmitt trigger) on all pins
- Bus hold circuitry on all user pins
- IEEE standard 1149.1 boundary scan (JTAG)
- Fast programming times
- Excellent pin retention during design changes
- High quality and reliability
- Guaranteed 10,000 program/erase cycles
- 20 year data retention
Description
The CoolRunner-II 64-macrocell device is designed for both
high performance and low power applications. This lends
power savings to high-end communication equipment and
speed to battery operated devices.
This device consists of four Function Blocks inter-con-
nected by a low power Advanced Interconnect Matrix (AIM).
The AIM feeds 40 inputs to each Function Block. The Func-
tion Blocks consist of a 40 by 56 p-term PLA and 16 macro-
cells which contain numerous configuration bits that allow
for combinational or registered modes of operation. Addi-
tionally, these registers can be globally reset or preset and
configured as a D or T flip-flop or as a D latch. There are
also multiple clock signals, both global and local product
term based, on a per macrocell basis. Output control sig-
nals include slew rate control, bus hold and open drain. An
additional Schmitt-trigger input is available on a per input
pin basis.
In addition to combinatorial and registered outputs, the reg-
isters may be configured as fast inputs.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as
a synchronous clock source. Global clocks are additionally
used to set or preset individual macrocell registers on
power up. Local clocks are generated in specific Function
Blocks and only available to macrocell registers in that
Function Block.
A DualEDGE flip-flop feature is also available on a per mac-
rocell basis. This feature allows performance where it is
needed without raising the total power consumption of the
entire device.
The CoolRunner-II 64-macrocell CPLD is I/O compatible
with standard LVTTL33 and LVCMOS18, 25, and 33 volts
(see Table 1).
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Refer to the CoolRunner鈩?II family data sheet for architec-
ture description.
Fast Zero Power Design Technology
All CoolRunner-II CPLDs employ Fast Zero Power鈩?(FZP),
a design technique that employs CMOS technology in both
the fabrication and design methodology. Xilinx CoolRun-
ner-II is fabricated on a 0.18 micron process technology
which is derived from leading edge FPGA product develop-
ment. CoolRunner-II design technology employs a cascade
of CMOS gates to implement sum of products instead of tra-
ditional sense amplifier methodology. Due to this FZP tech-
nology, Xilinx CoolRunner-II CPLDs achieve both high
performance and low power operation.
漏 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS092 (v1.0) December 19, 2001
Advance Product Specification
www.xilinx.com
1-800-255-7778
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