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XC17V02SERIES Datasheet

  • XC17V02SERIES

  • XC17V00 Series Configuration PROM

  • 13頁

  • ETC

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XC17V00 Series Configuration
PROM
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DS073 (v1.5) October 9, 2001
Advance Product Specification
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Available in compact plastic packages: VQ44, PC44,
PC20, VO8, and SO20
Programming support by leading programmer
manufacturers.
Design support using the Xilinx Alliance and
Foundation series software packages.
Dual configuration modes for the XC17V16 and
XC17V08 devices
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Serial slow/fast configuration (up to 33 Mb/s)
Parallel (up to 264 Mb/s at 33 MHz)
Features
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One-time programmable (OTP) read-only memory
designed to store configuration bitstreams of Xilinx
FPGA devices
Simple interface to the FPGA
Cascadable for storing longer or multiple bitstreams
Programmable reset polarity (active High or active
Low) for compatibility with different FPGA solutions
Low-power CMOS Floating Gate process
3.3V supply voltage
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Guaranteed 20 year life data retention
Description
Xilinx introduces the high-density XC17V00 family of config-
uration PROMs which provide an easy-to-use, cost-effec-
tive method for storing large Xilinx FPGA configuration
bitstreams. Initial devices in the 3.3V family are available in
16 Mb, 8 Mb, 4 Mb, 2 Mb, and 1 Mb densities. See
Figure 1
and
Figure 2
for simplified block diagrams of the XC17V00
family.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising clock edge, data appears on the PROM
DATA output pin that is connected to the FPGA DIN pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.
When the FPGA is in SelectMAP mode, an external oscilla-
tor will generate the configuration clock that drives the
PROM and the FPGA. After the rising CCLK edge, data are
available on the PROMs DATA (D0-D7) pins. The data will
be clocked into the FPGA on the following rising edge of the
CCLK. A free-running oscillator may be used to drive CCLK.
See
Figure 3.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.
For device programming, either the Xilinx Alliance or Foun-
dation series development system compiles the FPGA
design file into a standard Hex format, which is then trans-
ferred to most commercial PROM programmers.
漏 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS073 (v1.5) October 9, 2001
Advance Product Specification
www.xilinx.com
1-800-255-7778
1

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