音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

XC1701L(3.3V) Datasheet

  • XC1701L(3.3V)

  • Serial Configuration PROMs

  • 73.54KB

  • 10頁

  • XILINX   XILINX

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預覽

0
廬
XC1701L
(3.3V),
XC1701
(5.0V) and
XC17512L
(3.3V)
Serial Con鏗乬uration PROMs
0
5*
December 10, 1997 (Version 1.1)
Product Specification
Features
鈥?On-chip address counter, incremented by each rising
edge on the clock input
鈥?Simple interface to the FPGA; requires only one user
I/O pin
鈥?Cascadable for storing longer or multiple bitstreams
鈥?Programmable reset polarity (active High or active Low)
for compatibility with different FPGA solutions
鈥?Supports XC4000EX/XL fast con鏗乬uration mode (15.0
MHz)
鈥?Low-power CMOS Floating Gate process
鈥?Available in 5 V and 3.3 V versions
鈥?Available in compact plastic packages: 8-pin PDIP,
20-pin SOIC, and 20-pin PLCC.
鈥?Programming support by leading programmer
manufacturers.
鈥?Design support using the Xilinx Alliance and
Foundation series software packages.
Description
The XC1701L, XC1701 and XC17512L serial con鏗乬uration
PROMs (SCPs) provide an easy-to-use, cost-effective
method for storing Xilinx FPGA con鏗乬uration bitstreams.
When the FPGA is in master serial mode, it generates a
con鏗乬uration clock that drives the SCP. A short access time
after the rising clock edge, data appears on the SCP DATA
output pin that is connected to the FPGA DIN pin. The
FPGA generates the appropriate number of clock pulses to
complete the con鏗乬uration. Once con鏗乬ured, it disables the
SCP. When the FPGA is in slave mode, the SCP and the
FPGA must both be clocked by an incoming signal.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all SCPs in this chain
are interconnected. All devices are compatible and can be
cascaded with other members of the family.
For device programming, either the Xilinx Alliance or Foun-
dation series development system compiles the FPGA
design 鏗乴e into a standard Hex format, which is then trans-
ferred to the programmer.
V
CC
V
PP
GND
CE
RESET/
OE or
OE/
RESET
CLK
Address Counter
TC
CEO
EPROM
Cell
Matrix
Output
OE
DATA
X3185
Figure 1: Simpli鏗乪d Block Diagram (does not show programming circuit)
December 10, 1997 (Version 1.1)
5-1

XC1701L(3.3V)相關(guān)型號PDF文件下載

您可能感興趣的PDF文件資料

熱門IC型號推薦

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時間周一至周五
9:00-17:30

關(guān)注官方微信號，
第一時間獲取資訊。

建議反饋
返回頂部

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動力！意見一經(jīng)采納，將有感恩紅包奉上哦！