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X9401YV24I-2.7 Datasheet

  • X9401YV24I-2.7

  • Low Noise/Low Power/SPI Bus

  • 20頁

  • INTERSIL   INTERSIL

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廬
X9401
Low Noise/Low Power/SPI Bus
Data Sheet
September 23, 2005
FN8190.2
PRELIMINARY
Quad, 64 Tap, Digitally Controlled
Potentiometer (XDCP鈩?
FEATURES
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Quad鈥? separate pots, 64 taps/pot
Nonvolatile storage of wiper position
Four Nonvolatile Data Registers for Each Pot
16-bytes of EEPROM memory
SPI serial interface
R
Total
= 10k鈩?/div>
Wiper resistance = 150鈩?typical
Standby current < 1碌A(chǔ) (total package)
Operating current < 400碌A(chǔ) max.
V
CC
= 2.7V to 5V
Packages鈥?4 Ld TSSOP and SOIC
100 year data retention
Pb-free plus anneal available (RoHS compliant)
DESCRIPTION
The X9401 integrates 4 digitally controlled potentiome-
ters (XDCP) on a monolithic CMOS integrated
microcircuit.
The digitally controlled potentiometer is implemented
using 64 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI bus
interface. Each potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and 4 nonvola-
tile Data Registers (DR0:DR3) that can be directly writ-
ten to and read by the user. The contents of the WCR
controls the position of the wiper on the resistor array
through the switches. Power-up recalls the contents of
DR0 to the WCR.
The XDCP can be used as a three-terminal potentiom-
eter or as a two-terminal variable resistor in a wide
variety of applications including control, parameter
adjustments, and signal processing.
BLOCK DIAGRAM
V
CC
V
SS
R0 R1
Pot 0
Wiper
Counter
Register
(WCR)
V
H0
/R
H0
R0 R1
Wiper
Counter
Register
(WCR)
V
H2
/R
H2
HOLD
CS
SCK
SO
SI
A0
A1
WP
Interface
and
Control
Circuitry
Data
R2 R3
V
L0
/R
L0
V
W0
/R
W0
R2 R3
Resistor
Array
Pot 2
V
L2
/R
L2
V
W2
/R
W2
8
V
W1
/R
W1
R0 R1
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 1
V
H1
/R
H1
R0 R1
Wiper
Counter
Register
(WCR)
V
W3
/R
W3
V
H3
/R
H3
R2 R3
V
L1
/R
L1
R2 R3
Resistor
Array
Pot 3
V
L3
/R
L3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

X9401YV24I-2.7 產(chǎn)品屬性

  • 62

  • 集成電路 (IC)

  • 數(shù)據(jù)采集 - 數(shù)字電位器

  • XDCP™

  • 64

  • 2.5k

  • 4

  • 標準值 ±300 ppm/°C

  • 非易失

  • 6 線 SPI（芯片選擇，設(shè)備位址）

  • 2.7 V ~ 5.5 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 24-TSSOP（0.173"，4.40mm 寬）

  • 24-TSSOP

  • 管件

X9401YV24I-2.7相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    Low Noise/Low Power/SPI Bus
    INTERSIL
  • 英文版
    Quad Digitally Controlled Potentiometers (XDCP)
    XICOR
  • 英文版
    Low Noise/Low Power/SPI Bus
    INTERSIL [...
  • 英文版
    Quad Digitally Controlled Potentiometers (XDCP)
    XICOR [Xic...
  • 英文版
    Low Noise/Low Power/SPI Bus
    INTERSIL
  • 英文版
    Low Noise/Low Power/SPI Bus
    INTERSIL [...
  • 英文版
    Low Noise/Low Power/2-Wire Bus
    INTERSIL
  • 英文版
    Low Noise/Low Power/2-Wire Bus
    INTERSIL [...
  • 英文版
    Low Noise/Low Power/2-Wire Bus
    INTERSIL
  • 英文版
    Quad Digitally Controlled Potentiometers
    XICOR
  • 英文版
    Low Noise/Low Power/2-Wire Bus
    INTERSIL [...
  • 英文版
    Quad Digitally Controlled Potentiometers
    XICOR [Xic...
  • 英文版
    Quad Digitally Controlled Potentiometers
    INTERSIL [...
  • 英文版
    Quad, 64 Tap, Digitally Controlled Potentiometer
    INTERSIL [...
  • 英文版
    Quad Digitally Controlled Potentiometers
    INTERSIL [...
  • 英文版
    Digital Potentiometer
    ETC
  • 英文版
    Digital Potentiometer
  • 英文版
    Low Noise/Low Power/SPI Bus
    INTERSIL
  • 英文版
    Low Noise/Low Power/SPI Bus
    INTERSIL [...
  • 英文版
    Low Noise/Low Power/SPI Bus
    INTERSIL [...

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