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X86C64SM Datasheet

  • X86C64SM

  • E2 Micro-Peripheral

  • 12頁

  • XICOR   XICOR

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Preliminary Information
X86C64
Z8
廬
Microcontroller Family Compatible
64K
X86C64
E
2
Micro-Peripheral
DESCRIPTION
8192 x 8 Bit
FEATURES
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CONCURRENT READ WRITE
鈩?/div>
鈥擠ual Plane Architecture
Isolates Read/Write Functions
Between Planes
Allows Continuous Execution of Code
From One Plane While Writing in the Other
Plane
Multiplexed Address/Data Bus
鈥擠irect Interface to Popular 8-bit
Microcontrollers, e.g. Zilog Z8 Family
High Performance CMOS
鈥擣ast Access Time, 120 ns
鈥擫ow Power
60 mA Maximum Active
200
碌
A Maximum Standby
Software Data Protection
Block Protect Register
鈥擨ndividually Set Write Lock Out in 1K Blocks
Toggle Bit
鈥擡arly End of Write Detection
Page Mode Write
鈥擜llows up to 32 Bytes to be Written in
One Write Cycle
High Reliability
鈥擡ndurance: 10,000 Write Cycle
鈥擠ata Retention: 100 Years
The X86C64 is an 8K x 8 E
2
PROM fabricated with
advanced CMOS Textured Poly Floating Gate Technol-
ogy. The X86C64 features a Multiplexed Address and
Data bus allowing direct interface to a variety of popular
single-chip microcontrollers operating in expanded mul-
tiplexed mode without the need for additional interface
circuitry.
The X86C64 is internally configured as two indepen-
dent 4K x 8 memory arrays. This feature provides the
ability to perform nonvolatile memory updates in one
array and continue operation out of code stored in the
other array; effectively eliminating the need for an aux-
iliary memory device for code storage.
To write to the X86C64, a three byte command
sequence must precede the byte(s) being written. The
X86C64 also provides a second generation software
data protection scheme called Block Protect. Block
Protect can provide write lockout of the entire device or
selected 1K blocks. There are eight, 1K x 8 blocks that
can be write protected individually in any combination
required by the user. Block Protect, in addition to Write
Control input, allows the different segments of the
memory to have varying degrees of alterability in nor-
mal system operation.
FUNCTIONAL DIAGRAM
CE
R/W
DS
SEL
A8鈥揂11
CONTROL
LOGIC
X
D
E
C
O
D
E
WC
A12
SOFTWARE
DATA
PROTECT
A12
1K BYTES
1K BYTES
1K BYTES
1K BYTES
A12
M
U
X
1K BYTES
1K BYTES
1K BYTES
1K BYTES
AS
L
A
T
C
H
E
S
Y DECODE
I/O & ADDRESS LATCHES AND BUFFERS
A/D0鈥揂/D7
Z8
廬
is a registered trademark of Zilog Corporation
CONCURRENT READ WRITE
鈩?/div>
is a trademark of Xicor, Inc.
漏 Xicor, 1991 Patents Pending
3819-2.1 7/29/96 T0/C1/D1 SH
3819 FHD F02
1
Characteristics subject to change without notice

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