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X84641V20-2.5 Datasheet

  • X84641V20-2.5

  • uPort Saver EEPROM

  • 18頁

  • XICOR   XICOR

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A
PPLICATION
N
OTE
A V A I L A B L E
AN95 鈥?AN103 鈥?AN107
16K/64K/128K
X84161/641/129
碌
Port Saver EEPROM
DESCRIPTION
MPS
鈩?/div>
EEPROM
FEATURES
鈥?Up to 10MHz data transfer rate
鈥?25ns Read Access Time
鈥?Direct Interface to Microprocessors and
Microcontrollers
鈥擡liminates I/O port requirements
鈥擭o interface glue logic required
鈥擡liminates need for parallel to serial converters
鈥?Low Power CMOS
鈥?.8V鈥?.6V, 2.5V鈥?.5V and 5V
鹵10%
Versions
鈥擲tandby Current Less than 1碌A
鈥擜ctive Current Less than 1mA
鈥?Byte or Page Write Capable
鈥?2-Byte Page Write Mode
鈥?Typical Nonvolatile Write Cycle Time: 2ms
鈥?High Reliability
鈥?00,000 Endurance Cycles
鈥擥uaranteed Data Retention: 100 Years
The
碌
Port Saver memories need no serial ports or spe-
cial hardware and connect to the processor memory bus.
Replacing bytewide data memory, the
碌
Port Saver uses
bytewide memory control functions, takes a fraction of
the board space and consumes much less power.
Replacing serial memories, the
碌
Port Saver provides all
the serial bene鏗乼s, such as low cost, low power, low volt-
age, and small package size while releasing I/Os for
more important uses.
The
碌
Port Saver memory outputs data within 25ns of an
active read signal. This is less than the read access time
of most hosts and provides 鈥渘o-wait-state鈥?operation.
This prevents bottlenecks on the bus. With rates to 10
MHz, the
碌
Port Saver supplies data faster than required
by most host read cycle speci鏗乧ations. This eliminates
the need for software NOPs.
The
碌
Port Saver memories communicate over one line of
the data bus using a sequence of standard bus read and
write operations. This 鈥渂it serial鈥?interface allows the
碌
Port Saver to work well in 8-bit, 16 bit, 32-bit, and 64-bit
systems.
A Write Protect (WP) pin prevents inadvertent writes to
the memory.
Xicor EEPROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data reten-
tion is greater than 100 years.
BLOCK DIAGRAM
System Connection
碌P
碌C
DSP
ASIC
RISC
Ports
Saved
P0/CS
P1/CLK
P2/DI
P3/DO
A15
WP
Internal Block Diagram
MPS
H.V. GENERATION
TIMING & CONTROL
A0
D7
D0
OE
WE
CE
I/O
OE
WE
COMMAND
DECODE
AND
CONTROL
LOGIC
EEPROM
ARRAY
X
DEC
16K x 8
8K x 8
2K x 8
Y DECODE
DATA REGISTER
7008 FRM F02.1
漏
Xicor, Inc. 1994, 1997Patents Pending
7008-1.2 8/26/97 T2/C0/D0 SH
Characteristics subject to change without notice
1

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