鈩?/div>
EEPROM
FEATURES
鈥?Up to 10MHz data transfer rate
鈥?25ns Read Access Time
鈥?Direct Interface to Microprocessors and
Microcontrollers
鈥擡liminates I/O port requirements
鈥擭o interface glue logic required
鈥擡liminates need for parallel to serial converters
鈥?Low Power CMOS
鈥?.5V鈥?.5V and 5V 鹵10% Versions
鈥擲tandby Current Less than 1碌A(chǔ)
鈥擜ctive Current Less than 3mA
鈥?Byte or Page Write Capable
鈥?4-Byte Page Write Mode
鈥?Typical Nonvolatile Write Cycle Time: 2ms
鈥?High Reliability
鈥?,000,000 Endurance Cycles
鈥擥uaranteed Data Retention: 100 Years
鈥?Small Packages Options
鈥?, 16-Lead SOIC Packages
鈥?4-Lead TSSOP Packages
鈥?-Lead XBGA Packages
The 碌Port Saver memories need no serial ports or spe-
cial hardware and connect to the processor memory bus.
Replacing bytewide data memory, the 碌Port Saver uses
bytewide memory control functions, takes a fraction of
the board space and consumes much less power.
Replacing serial memories, the 碌Port Saver provides all
the serial bene鏗乼s, such as low cost, low power, low volt-
age, and small package size while releasing I/Os for
more important uses.
The 碌Port Saver memory outputs data within 25ns of an
active read signal. This is less than the read access time
of most hosts and provides 鈥渘o-wait-state鈥?operation.
This prevents bottlenecks on the bus. With rates to 10
MHz, the 碌Port Saver supplies data faster than required
by most host read cycle speci鏗乧ations. This eliminates
the need for software NOPs.
The 碌Port Saver memories communicate over one line
of the data bus using a sequence of standard bus read
and write operations. This 鈥渂it serial鈥?interface allows the
碌Port Saver to work well in 8-bit, 16 bit, 32-bit, and 64-bit
systems.
A Write Protect (WP) pin prevents inadvertent writes to
the memory.
Xicor EEPROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data reten-
tion is greater than 100 years.
BLOCK DIAGRAM
System Connection
碌P
碌C
DSP
ASIC
RISC
Ports
Saved
P0/CS
P1/CLK
P2/DI
P3/DO
A15
WP
Internal Block Diagram
MPS
H.V. GENERATION
TIMING & CONTROL
A0
D7
D0
OE
WE
CE
I/O
OE
WE
COMMAND
DECODE
AND
CONTROL
LOGIC
EEPROM
ARRAY
X
DEC
32K x 8
Y DECODE
DATA REGISTER
漏
Xicor, Inc. 1998 Patents Pending
4005 1 8/24/99 WW
1
Characteristics subject to change without notice