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X84256S825 Datasheet

  • X84256S825

  • Serial EEPROM

  • 13頁(yè)

  • ETC

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256K
X84256
碌Port Saver EEPROM
DESCRIPTION
MPS
鈩?/div>
EEPROM
FEATURES
鈥?10MHz data transfer rate
鈥?30ns read access time
鈥?Direct interface to microprocessors and micro-
controllers
鈥擡liminates I/O port requirements
鈥擭o interface glue logic required
鈥擡liminates need for parallel to serial converters
鈥?Low power CMOS
鈥?.5V鈥?.6V
鈥擲tandby current less than 1碌A(chǔ)
鈥擜ctive current less than 3mA
鈥?Byte or page write capable
鈥?4-byte page write mode
鈥?Typical nonvolatile write cycle time: 2ms
鈥?High reliability
鈥?,000,000 endurance cycles
鈥擥uaranteed data retention: 100 years
鈥?Small packages options
鈥?-lead SOIC package
鈥?4-lead TSSOP package
鈥?-lead XBGA package
The 碌Port Saver memories need no serial ports or
special hardware and connect to the processor mem-
ory bus. Replacing bytewide data memory, the 碌Port
Saver uses bytewide memory control functions, takes
a fraction of the board space and consumes much less
power. Replacing serial memories, the 碌Port Saver
provides all the serial bene鏗乼s, such as low cost, low
power, low voltage, and small package size while
releasing I/Os for more important uses.
The 碌Port Saver memory outputs data within 30ns of
an active read signal. This is less than the read access
time of most hosts and provides 鈥渘o-wait-state鈥?opera-
tion. This prevents bottlenecks on the bus. With 10
MHz, the 碌Port Saver supplies data faster than
required by most host read cycle speci鏗乧ations. This
eliminates the need for software NOPs.
The 碌Port Saver memories communicate over one line
of the data bus using a sequence of standard bus read
and write operations. This 鈥渂it serial鈥?interface allows
the 碌Port Saver to work well in 8-bit, 16 bit, 32-bit, and
64-bit systems.
A Write Protect (WP) pin prevents inadvertent writes to
the memory.
Xicor EEPROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data
retention is greater than 100 years.
BLOCK DIAGRAM
Internal Block Diagram
System Connection
碌P
碌C
DSP
ASIC
RISC
D0
Ports
Saved
P0/CS
P1/CLK
P2/DI
P3/DO
OE
WE
Y Decode
Data Register
A0
D7
CE
I/O
OE
WE
Command
Decode
and
Control
Logic
X
DEC
EEPROM
Array
32K x 8
A15
WP
MPS
H.V. Generation
Timing & Control
REV 1.1 11/22/00
www.xicor.com
Characteristics subject to change without notice.
1 of 13

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