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X68C75PM Datasheet

  • X68C75PM

  • Port Expander and E2 Memory

  • 126.13KB

  • 26頁

  • XICOR   XICOR

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A
PPLICATION
N
OTES
A V A I L A B L E
AN62 鈥?AN64
X68C75 SLIC
鈥?/div>
廬
AN66 鈥?AN74
E
2
SLIC
X68C75 SLIC
廬
E
2
Microperipheral
Port Expander and
E
2
Memory
鈥?High Performance CMOS
鈥擣ast Access Time, 120ns
鈥擫ow Power
鈥?60mA Active
鈥?100
碌
A Standby
鈥?PDIP, PLCC, and TQFP Packaging Available
DESCRIPTION
The X68C75 is a highly integrated peripheral for the
68HC11 family of microcontrollers. The device inte-
grates 8K-bytes of 5V byte-alterable nonvolatile memory,
2 bidirectional 8-bit ports, 16 general purpose registers,
programmable internal address decoding and a multi-
plexed address and data bus.
The 5V byte-alterable nonvolatile memory can be used
as program storage, data storage, or a combination of
both. The memory array is separated into two 4K-byte
sections which allows read accesses to one section
while a write operation is taking place in the other
section. The nonvolatile memory also features Software
Data Protection to protect the contents during power
transitions, and an advanced Block Protect register
which allows individual blocks of the memory to be
configured as read-only or read/write.
FEATURES
鈥?Highly Integrated Microcontroller Peripheral
鈥?K x 8 E
2
Memory
鈥? x 8 General Purpose Bidirectional I/O Ports
鈥?6 x 8 General Purpose Registers
鈥擨ntegerated Interrupt Controller Module
鈥擨nternal Programmable Address Decoding
鈥?Self Loading Integrated Code (SLIC)
鈥擮n-Chip BIOS and Boot Loader
鈥擨BM/PC Based Interface Software(XSLIC)
鈥?Concurrent Read During Write
鈥擠ual Plane Architecture
鈥?Isolates Read/Write Functions Between
Planes
鈥?Allows Continuous Execution Of Code
From One Plane While Writing In The
Other Plane
鈥?Multiplexed Address/Data Bus
鈥擠irect Interface to Popular 68HC11 Family of
Microcontrollers
鈥?Software Data Protection
鈥擯rotect Entire Array During Power-up/-down
鈥?Block Lock鈩?Data Protection
鈥擲et Write Lockout in 1K Blocks
鈥?Toggle Bit Polling
PIN CONFIGURATIONS
DIP
RESET
A12
WC
SEL
STRA
A15
NC
A14
A13
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
NC
A/D0
A/D1
A/D2
A/D3
A/D4
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
X68C75
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VCC
R/W
PLCC
TQFP
STRA
RESET
VCC
SEL
A15
WC
A12
AS
A8
A9
AS
A8
A9
A11
NC
IRQ
STRB
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
NC
E
A10
CE
A/D7
A/D6
A/D5
2899 ILL F01
INDEX
CORNER
A14
A13
PA7
PA6
PA5
PA4
PA3
4
6
7
8
9
10
11
12
13
14
15
16
17
5
4
3
2
1 44 43 42 41 40
39
38
37
36
A11
IRQ
STRB
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
R/W
X68C75
SLIC
35
34
33
32
31
30
29
33
PA2
PA1
PA0
A/D0
18 19 20 21 22 23 24 25 26 27 28
A/D1
A/D2
A/D3
A/D4
VSS
A/D5
A/D6
A/D7
A10
CE
E
2899 ILL F02.3
Concurrent Read During Write, Block Lock, and SLIC
廬
E
2
are registered trademarks of Xicor, Inc.
漏Xicor, Inc. 1994, 1995, 1996 Patents Pending
2899-2.1 4/11/97 T0/C0/D1 SH
1
Characteristics subject to change without notice

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