鈥?/div>
鈥擨n circuit programmable ROM mode
Minimize EEPROM programming time
鈥?4 byte page write mode
鈥擲elf-timed write cycle
鈥?ms write cycle time (typical)
10MHz SPI interface modes (0,0 & 1,1)
2.7V to 5.5V power supply operation
Available packages 鈥?20-lead TSSOP
DESCRIPTION
This device combines power-on reset control, battery
switch circuit, watchdog timer, supply voltage supervi-
sion, secondary voltage supervision, block lock protect
and serial EEPROM in one package. This combination
lowers system cost, reduces board space require-
ments, and increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
V
OUT
V2MON
V2 Monitor
Logic
+
V2FAIL
V
TRIP2
-
Watchdog Transition
Detector
WP
SO
SI
Data
Register
Command
Decode, Test
& Control
Logic
Protect Logic
Status
Register
EEPROM Array
Watchdog
Timer Reset
WDO
RESET
X-Decoder
Reset &
Watchdog
Timebase
BATT-ON
SCK
CS
512 X 128
V
OUT
V
BATT
V
CC
(V1MON)
System
Battery
Switch
+
RESET/MR
V
OUT
V
CC
Monitor
Logic
V
TRIP1
-
Power-on,
Low Voltage
Reset
Generation
LOWLINE
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832
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Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.