鈩?/div>
protection
鈥擨n circuit programmable ROM mode
鈥?2MHz SPI interface modes (0,0 & 1,1)
鈥?Minimize EEPROM programming time
鈥?2-byte page write mode
鈥擲elf-timed write cycle
鈥?ms write cycle time (typical)
鈥?2.7V to 5.5V and 4.5V to 5.5V power supply
operation
鈥?Available packages
鈥?4-lead TSSOP, 8-lead SOIC
BLOCK DIAGRAM
WP
SI
SO
SCK
CS
Data
Register
Command
Decode &
Control
Logic
Protect Logic
Status
Register
EEPROM Array
8Kbits
8Kbits
16Kbits
DESCRIPTION
These devices combine three popular functions, Power-
on Reset Control, Supply Voltage Supervision, and
Block Lock Protect Serial EEPROM Memory in one
package. This combination lowers system cost, reduces
board space requirements, and increases reliability.
Applying power to the device activates the power on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The device鈥檚 low V
CC
detection circuitry protects the
user鈥檚 system from low voltage conditions by holding
RESET/RESET active when V
CC
falls below a mini-
mum V
CC
trip point. RESET/RESET remains asserted
until V
CC
returns to proper operating level and stabi-
lizes. Five industry standard V
TRIP
thresholds are
available, however, Xicor鈥檚 unique circuits allow the
threshold to be reprogrammed to meet custom
requirements or to 鏗乶e-tune the threshold in applica-
tions requiring higher precision.
Reset
Timebase
RESET/RESET
V
CC
V
TRIP
+
-
Power on and
Low Voltage
Reset
Generation
X5328 = RESET
X5329 = RESET
REV 1.1.1 3/6/01
www.xicor.com
Characteristics subject to change without notice.
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