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X5325V14Z-2.7 Datasheet

  • X5325V14Z-2.7

  • CPU Supervisor with 32Kb SPI EEPROM

  • 21頁

  • INTERSIL   INTERSIL

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廬
X5323, X5325
(Replaces X25323, X25325)
Data Sheet
October 27, 2005
FN8131.1
CPU Supervisor with 32Kb SPI EEPROM
FEATURES
鈥?Selectable watchdog timer
鈥?Low V
CC
detection and reset assertion
鈥擣ive standard reset threshold voltages
鈥擱e-program low V
CC
reset threshold voltage
using special programming sequence
鈥擱eset signal valid to V
CC
= 1V
鈥?Determine watchdog or low voltage reset with a
volatile flag bit
鈥?Long battery life with low power consumption
鈥?lt;50碌A(chǔ) max standby current, watchdog on
鈥?lt;1碌A(chǔ) max standby current, watchdog off
鈥?lt;400碌A(chǔ) max active current during read
鈥?32Kbits of EEPROM
鈥?Built-in inadvertent write protection
鈥擯ower-up/power-down protection circuitry
鈥擯rotect 0, 1/4, 1/2 or all of EEPROM array with
Block Lock
鈩?/div>
protection
鈥擨n circuit programmable ROM mode
鈥?2MHz SPI interface modes (0,0 & 1,1)
鈥?Minimize EEPROM programming time
鈥?2-byte page write mode
鈥擲elf-timed write cycle
鈥?ms write cycle time (typical)
鈥?2.7V to 5.5V and 4.5V to 5.5V power supply
operation
鈥?Available packages
鈥?4 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
鈥?Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
Watchdog Transition
Detector
WP
SI
SO
SCK
CS/WDI
Data
Register
Command
Decode &
Control
Logic
V
CC
Threshold
Reset Logic
Protect Logic
DESCRIPTION
These devices combine four popular functions, Power-on
Reset Control, Watchdog Timer, Supply Voltage
Supervision, and Block Lock Protect Serial EEPROM
Memory in one package. This combination lowers
system cost, reduces board space requirements, and
increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the
RESET/RESET signal. The user selects the interval
from three preset values. Once selected, the interval
does not change, even after cycling the power.
The device鈥檚 low V
CC
detection circuitry protects the
user鈥檚 system from low voltage conditions, resetting the
system when V
CC
falls below the minimum V
CC
trip
point. RESET/RESET is asserted until V
CC
returns to
proper operating level and stabilizes. Five industry stan-
dard V
TRIP
thresholds are available, however, Intersil鈥檚
unique circuits allow the threshold to be reprogrammed
to meet custom requirements or to fine-tune the thresh-
old for applications requiring higher precision.
Watchdog
Timer Reset
RESET/RESET
Status
Register
8Kbits
8Kbits
16Kbits
EEPROM Array
Reset &
Watchdog
Timebase
X5323 = RESET
X5325 = RESET
V
CC
V
TRIP
+
-
Power-on and
Low Voltage
Reset
Generation
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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    CPU Supervisor with 32Kb SPI EEPROM
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    CPU Supervisor with 32Kb SPI EEPROM
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    CPU Supervisor with 32Kb SPI EEPROM
    INTERSIL
  • 英文版
    CPU Supervisor with 32Kb SPI EEPROM
    INTERSIL [...
  • 英文版
    CPU Supervisor with 32Kbit SPI EEPROM
    INTERSIL
  • 英文版
    CPU Supervisor with 32Kbit SPI EEPROM
    INTERSIL [...
  • 英文版
    CPU Supervisor with 32Kbit SPI EEPROM
    INTERSIL
  • 英文版
    CPU Supervisor with 32Kbit SPI EEPROM
    INTERSIL [...
  • 英文版
    CPU Supervisor with 32Kb SPI EEPROM
    INTERSIL
  • 英文版
    CPU Supervisor with 32Kb SPI EEPROM
    INTERSIL [...
  • 英文版
    CPU Supervisor with 32Kb SPI EEPROM
    INTERSIL
  • 英文版
    CPU Supervisor with 32Kb SPI EEPROM
    INTERSIL [...
  • 英文版
    CPU Supervisor with 32Kbit SPI EEPROM
    INTERSIL
  • 英文版
    CPU Supervisor with 32Kbit SPI EEPROM
    INTERSIL [...
  • 英文版
    CPU Supervisor with 32Kbit SPI EEPROM
    INTERSIL
  • 英文版
    CPU Supervisor with 32Kbit SPI EEPROM
    INTERSIL [...
  • 英文版
    CPU Supervisor with 32Kb SPI EEPROM
    INTERSIL
  • 英文版
    CPU Supervisor with 32Kb SPI EEPROM
    INTERSIL [...
  • 英文版
    CPU Supervisor with 32Kb SPI EEPROM
    INTERSIL
  • 英文版
    CPU Supervisor with 32Kb SPI EEPROM
    INTERSIL [...

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