X5083
CPU Supervisor with 8Kbit SPI EEPROM
FEATURES
鈥?Low V
CC
detection and reset assertion
鈥擣our standard reset threshold voltages
4.63V, 4.38V, 2.93V, 2.63V
鈥擱e-program low V
CC
reset threshold voltage
using special programming sequence.
鈥擱eset signal valid to V
CC
= 1V
鈥?Selectable time out watchdog timer
鈥?Long battery life with low power consumption
鈥?lt;50碌A max standby current, watchdog on
鈥?lt;1碌A max standby current, watchdog off
鈥?lt;400碌A max active current during read
鈥?8Kbits of EEPROM
鈥?Save critical data with Block Lock
鈩?/div>
memory
鈥擝lock lock first or last page, any 1/4 or lower 1/2
of EEPROM array
鈥?Built-in inadvertent write protection
鈥擶rite enable latch
鈥擶rite protect pin
鈥?SPI Interface - 3.3MHz clock rate
鈥?Minimize programming time
鈥?6 byte page write mode
鈥?ms write cycle time (typical)
鈥?SPI modes (0,0 & 1,1)
鈥?Available packages
鈥?-lead TSSOP, 8-lead SOIC, 8-Lead PDIP
BLOCK DIAGRAM
POR and Low
Voltage Reset
Generation
Reset & Watchdog
Timebase
Watchdog
Transition
Detector
Watchdog
Timer
Reset
APPLICATIONS
鈥?Communications Equipment
鈥擱outers, Hubs, Switches
鈥擲et Top Boxes
鈥?Industrial Systems
鈥擯rocess Control
鈥擨ntelligent Instrumentation
鈥?Computer Systems
鈥擠esktop Computers
鈥擭etwork Servers
鈥?Battery Powered Equipment
Typical Application
2.7-5.0V
VCC
VCC
uC
X5083
RESET
CS
SCK
SI
SO
WP
VSS
10K
RESET
SPI
VSS
V
CC
V
TRIP
+
RESET (X5083)
-
X5083
Standard V
TRIP
Level
4.63V (+/-2.5%)
4.38V (+/-2.5%)
Suffix
-4.5A
-4.5
-2.7A
-2.7
CS/WDI
SI
SO
SCK
WP
Command
Decode &
Control
Logic
Protect Logic
Status
Register
EEPROM
Array
8Kbits
2.93V (+/-2.5%)
2.63V (+/-2.5%)
See 鈥淥rdering Information鈥?on page 21 for
more details
For Custom Settings, call Xicor.
REV 1.1.6 6/25/02
www.xicor.com
Characteristics subject to change without notice.
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