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X5083V8-4.5A Datasheet

  • X5083V8-4.5A

  • CPU Supervisor with 9Kbit SPI EEPROM

  • 348.02KB

  • 20頁

  • INTERSIL   INTERSIL

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X5083
Data Sheet
September 16, 2005
FN8127.2
CPU Supervisor with 8Kbit SPI EEPROM
This device combines four popular functions, Power-on Reset
Control, Watchdog Timer, Supply Voltage Supervision, and
Block Lock Serial EEPROM Memory in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
Applying power to the device activates the power-on reset
circuit which holds RESET active for a period of time. This
allows the power supply and oscillator to stabilize before the
processor can execute code.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontroller fails to
restart a timer within a selectable time out interval, the device
activates the RESET signal. The user selects the interval
from three preset values. Once selected, the interval does
not change, even after cycling the power.
The device鈥檚 low V
CC
detection circuitry protects the user鈥檚
system from low voltage conditions, resetting the system
when V
CC
falls below the minimum V
CC
trip point. RESET is
asserted until V
CC
returns to the proper operating level and
stabilizes. Five industry standard V
TRIP
thresholds are
available, however, Intersil鈥檚 unique circuits allow the threshold
to be reprogrammed to meet custom requirements or to fine-
tune the threshold for applications requiring higher precision.
Features
鈥?Low V
CC
detection and reset assertion
- Four standard reset threshold voltages
4.63V, 4.38V, 2.93V, 2.63V
- Re-program low V
CC
reset threshold voltage using
special programming sequence
- Reset signal valid to V
CC
= 1V
鈥?Selectable time out watchdog timer
鈥?Long battery life with low power consumption
- <50碌A(chǔ) max standby current, watchdog on
- <1碌A(chǔ) max standby current, watchdog off
- <400碌A(chǔ) max active current during read
鈥?8Kbits of EEPROM
鈥?Save critical data with Block Lock
鈩?/div>
memory
- Block lock first or last page, any 1/4 or lower 1/2 of
EEPROM array
鈥?Built-in inadvertent write protection
- Write enable latch
- Write protect pin
鈥?SPI Interface - 3.3MHz clock rate
鈥?Minimize programming time
- 16 byte page write mode
- 5ms write cycle time (typical)
鈥?SPI modes (0,0 & 1,1)
Pinouts
8 Ld TSSOP
RESET
V
CC
CS/WDI
SO
1
2
3
4
8
7
6
5
SCK
SI
V
SS
WP
鈥?Available packages
- 8 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
鈥?Pb-free plus anneal available (RoHS compliant)
X5083
Applications
8 Ld SOIC, 8 Ld PDIP
CS/WDI
SO
WP
V
SS
1
8
V
CC
RESET
SCK
SI
鈥?Communications Equipment
- Routers, Hubs, Switches
- Set Top Boxes
鈥?Industrial Systems
- Process Control
- Intelligent Instrumentation
鈥?Computer Systems
- Desktop Computers
- Network Servers
鈥?Battery Powered Equipment
2
7
X5083 6
3
4
5
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

X5083V8-4.5A 產(chǎn)品屬性

  • 100

  • 集成電路 (IC)

  • PMIC - 監(jiān)控器

  • -

  • 簡單復(fù)位/加電復(fù)位

  • 1

  • -

  • 低有效

  • 最小為 100 ms

  • 4.63V

  • 0°C ~ 70°C

  • 表面貼裝

  • 8-TSSOP（0.173"，4.40mm 寬）

  • 8-TSSOP

  • 管件

X5083V8-4.5A相關(guān)型號PDF文件下載

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  • 英文版
    CPU Supervisor with 9Kbit SPI EEPROM
    INTERSIL
  • 英文版
    CPU Supervisor with 8Kbit SPI EEPROM
    XICOR
  • 英文版
    CPU Supervisor with 8Kbit SPI EEPROM
    XICOR [Xic...
  • 英文版
    CPU Supervisor with 9Kbit SPI EEPROM
    INTERSIL [...
  • 英文版
    CPU Supervisor with 9Kbit SPI EEPROM
    INTERSIL
  • 英文版
    CPU Supervisor with 8Kbit SPI EEPROM
    XICOR
  • 英文版
    CPU Supervisor with 8Kbit SPI EEPROM
    XICOR [Xic...
  • 英文版
    CPU Supervisor with 9Kbit SPI EEPROM
    INTERSIL [...
  • 英文版
    CPU Supervisor with 9Kbit SPI EEPROM
    INTERSIL
  • 英文版
    CPU Supervisor with 9Kbit SPI EEPROM
    INTERSIL [...
  • 英文版
    CPU Supervisor with 8Kbit SPI EEPROM
    INTERSIL [...
  • 英文版
    CPU Supervisor with 9Kbit SPI EEPROM
    INTERSIL
  • 英文版
    CPU Supervisor with 8Kbit SPI EEPROM
    XICOR
  • 英文版
    CPU Supervisor with 8Kbit SPI EEPROM
    XICOR [Xic...
  • 英文版
    CPU Supervisor with 9Kbit SPI EEPROM
    INTERSIL [...
  • 英文版
    CPU Supervisor with 9Kbit SPI EEPROM
    INTERSIL
  • 英文版
    CPU Supervisor with 9Kbit SPI EEPROM
    INTERSIL [...
  • 英文版
    CPU Supervisor with 8Kbit SPI EEPROM
    XICOR
  • 英文版
    CPU Supervisor with 9Kbit SPI EEPROM
    INTERSIL
  • 英文版
    CPU Supervisor with 8Kbit SPI EEPROM
    XICOR [Xic...

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