音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

X5001P-4.5A Datasheet

  • X5001P-4.5A

  • CPU Supervisor

  • 18頁

  • INTERSIL   INTERSIL

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

廬
X5001
Data Sheet
April 6, 2005
FN8125.0
CPU Supervisor
FEATURES
鈥?200ms power-on reset delay
鈥?Low V
CC
detection and reset assertion
鈥擣ive standard reset threshold voltages
鈥擜djust low V
CC
reset threshold voltage using
special programming sequence
鈥擱eset signal valid to V
CC
= 1V
鈥?Selectable nonvolatile watchdog timer
鈥?.2, 0.6, 1.4 seconds
鈥擮ff selection
鈥擲elect settings through software
鈥?Long battery life with low power consumption
鈥?lt;50碌A(chǔ) max standby current, watchdog on
鈥?lt;1碌A(chǔ) max standby current, watchdog off
鈥?2.7V to 5.5V operation
鈥?SPI mode 0 interface
鈥?Built-in inadvertent write protection
鈥擯ower-up/power-down protection circuitry
鈥擶atchdog change latch
鈥?High reliability
鈥?Available packages
鈥?-lead TSSOP
鈥?-lead SOIC
鈥? pin PDIP
DESCRIPTION
This device combines three popular functions, Power-
on Reset, Watchdog Timer, and Supply Voltage
Supervision in one package. This combination lowers
system cost, reduces board space requirements, and
increases reliability.
The watchdog timer provides an independent protec-
tion mechanism for microcontrollers. During a system
failure, the device will respond with a RESET signal
after a selectable time out interval. The user selects the
interval from three preset values. Once selected, the
interval does not change, even after cycling the power.
The user鈥檚 system is protected from low voltage condi-
tions by the device鈥檚 low V
CC
detection circuitry. When
V
CC
falls below the minimum V
CC
trip point, the system
is reset. RESET is asserted until V
CC
returns to proper
operating levels and stabilizes. Five industry standard
V
TRIP
thresholds are available, however, Intersil鈥檚
unique circuits allow the threshold to be reprogrammed
to meet custom requirements or to fine-tune the thresh-
old for applications requiring higher precision.
The device utilizes Intersil鈥檚 proprietary Direct Write
鈩?/div>
cell for the watchdog timer control bits and the V
TRIP
storage element, providing a minimum endurance of
100,000 write cycles and a minimum data retention of
100 years.
BLOCK DIAGRAM
Watchdog
Transition
Detector
SI
SO
SCK
CS/WDI
Data
Register
Command
Decode &
Control
Logic
Power-on/
Low Voltage
REset
+
Watchdog
Timer
RESET
Reset &
Watchdog
Timebase
V
CC
V
TRIP
Generation
-
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

X5001P-4.5A相關(guān)型號PDF文件下載

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時間周一至周五
9:00-17:30

關(guān)注官方微信號，
第一時間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動力！意見一經(jīng)采納，將有感恩紅包奉上哦！