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X4C105V20I Datasheet

  • X4C105V20I

  • CPU Supervisor with NOVRAM and Output Ports

  • 19頁

  • INTERSIL   INTERSIL

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廬
X4C105
4K, NOVRAM/EEPROM
Data Sheet
March 18, 2005
FN8124.0
CPU Supervisor with NOVRAM and
Output Ports
FEATURES
鈥?4Kbit serial EEPROM
鈥?00kHz serial interface speed
鈥?6-byte page write mode
鈥?One nibble NOVRAM
鈥?20ns NOVRAM access speed
鈥擜UTOSTORE
鈥擠irect/bus access of NOVRAM bits
鈥?Four output ports
鈥?Operates at 3.3V 鹵 10%
鈥?Low voltage reset when V
CC
< 3V
鈥?% accurate thresholds available
鈥擮utput signal shows low voltage condition
鈥擜ctivates NOVRAM AUTOSTORE
鈥擨nternal block on EEPROM operation
鈥?Max EEPROM/NOVRAM nonvolatile write cycle:
5ms
鈥?High reliability
鈥?,000,000 endurance cycles
鈥擥uaranteed data retention: 100 years
鈥?20-lead TSSOP package
DESCRIPTION
The low voltage X4C105 combines several functions
into one device. The first is a 2-wire, 4Kbit serial
EEPROM memory with write protection. A Write Pro-
tect (WP) pin provides hardware protection for the
upper half of this memory against inadvertent writes.
A one nibble NOVRAM is provided and occupies a sin-
gle location. This allows access of 4-bits in a single
150ns cycle. This is useful for tracking system opera-
tion or process status. The NOVRAM memory is com-
pletely isolated from the serial memory section.
A low voltage detect circuit activates a RESET pin
when V
CC
drops below 3V. This signal also blocks
new read or write operations and initiates a NOVRAM
AUTOSTORE. The AUTOSTORE operation is pow-
ered by an external capacitor to ensure that the value
in the NOVRAM is always maintained in the event of a
power failure.
The four NOVRAM bits also appear on four separate
output pins to allow continuous control of external cir-
cuitry, such as ASICs.
Intersil EEPROMs are designed and tested for appli-
cations requiring extended endurance. Inherent data
retention is greater than 100 years.
BLOCK DIAGRAM
WP
Write Control Logic
HV Generation
Timing and Control
EEPROM
Memory
Static RAM
Memory
4Kbits
Output
Buffers
and
Latches
O0
O1
O2
O3
D0
D1
D2
D3
CE
OE
WE
CAP
V
CC
V
SS
RESET
Command
Decode
and
Control
Logic
X Decoder
SCL
SDA
S1
S2
EEPROM
Array
I/O
Buffers
Y Decoder
Data Register
Low Voltage Detect
Power-on Reset
Control
Logic
and
Timing
Voltage
Monitor
Supply
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

X4C105V20I 產(chǎn)品屬性

  • 75

  • 集成電路 (IC)

  • PMIC - 監(jiān)控器

  • -

  • 簡單復位/加電復位

  • 1

  • 開路漏極或開路集電極

  • 低有效

  • 最小為 100 ms

  • 2.875V

  • -40°C ~ 85°C

  • 表面貼裝

  • 20-TSSOP（0.173"，4.40mm 寬）

  • 20-TSSOP

  • 管件

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