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X46402V8E-3.1A Datasheet

  • X46402V8E-3.1A

  • Dual Voltage CPU Supervisor with 64K Password Protected EEPR...

  • 23頁

  • XICOR   XICOR

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Preliminary Information
64K
X46402
Dual Voltage CPU Supervisor with 64K Password Protected EEPROM
DESCRIPTION
The X46402 combines several functions into one device.
The 鏗乺st is a dual voltage CPU supervisor plus 64Kbit
serial EEPROM memory with password protected write
and read operations. The size of the password protected
area is selectable by 3 control bits. A Write Protect (WP)
pin in conjunction with a WPEN bit provides hardware
OTP control of the con鏗乬uration of the array. Password
protected areas require 64 bit read or write passwords
prior to access. The eighth illegal password entry
(regardless of the number of correct entries) sets an OTP
tamper bit. This bit is one of the 32 bits in the Device ID.
A secondary voltage monitor circuit activates a V2FAIL
pin when the secondary supply voltage drops below a
V2trip voltage. This circuit is primarily intended to detect
the immediate loss of the battery supply.
A low Vcc voltage detect circuit activates a RESET pin
when Vcc drops below a V
TRIP
voltage. This signal also
blocks read or write operations.
A watchdog timer with the time period controlled by three
bits provides several possible time out periods from
150ms to 1 minute.
FEATURES
鈥?Dual Voltage Detection and Reset Assertion
鈥擫ow Vcc Monitor
鈥擫ow V2MON Monitor
鈥擫ow Vcc Block of EEPROM Writes
鈥擱ESET Signal Valid down to Vcc=1V
鈥?Selectable Watchdog Timer
鈥?50ms, 450ms, 1s, 5s, 10s, 20s, 1min, OFF
鈥?Volatile Flag shows Watchdog/Low Voltage Reset
鈥?64kbit 2-wire Serial EEPROM
鈥?MHz Serial Interface speed
鈥?4-Byte Page Write Mode
鈥?Two 64-Byte OTP memory blocks
鈥擱equires 64-bit OTP password to write
鈥?Adjustable size Password Protected Array
鈥?4 Bit Read and Write Array Passwords
鈥擭on-password protected array area
鈥?8 count tamper counter for invalid passwords
鈥?Operates at 2.5-3.7V
鈥?8L TSSOP package
Functional Diagram
WP
Write Control
Password Logic
HV Generation
Timing and Control
WATCHDOG
TIMER RESET
RESET &
WATCHDOG
TIMEBASE
RESET
SCL
SDA
Command
Decode
and
Control
Logic
EEPROM
Array (64Kbits)
X Decoder
Write Password Area
(Bytes)
(64, 128, 256, 512,
2K, 4K, All, None)
No Password Area
Control
OTP array 1
OTP array 2
Passwords
Y Decoder
Data Register
POWER ON AND
LOW VOLTAGE
RESET
GENERATION
V2FAIL
+
-
V2MON
V
2TRIP
(Vcc) Control Signal
+
-
Vcc
V
TRIP
漏
Xicor, Inc. 1994, 1995, 1996, 1998 Patents Pending
9900-3003 5 1/11/00 CM
1
Characteristics subject to change without notice

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