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X40420V14I-C Datasheet

  • X40420V14I-C

  • Dual Voltage Monitor with Integrated CPU Supervisor and Syst...

  • 25頁

  • INTERSIL   INTERSIL

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廬
X40420, X40421
4kbit EEPROM
Data Sheet
March 28, 2005
FN8117.0
PRELIMINARY
Dual Voltage Monitor with Integrated CPU
Supervisor and System Battery Switch
FEATURES
鈥?Dual voltage detection and reset assertion
鈥擳hree standard reset threshold settings
(4.6V/2.9V, 4.6V/2.6V, 2.9V/1.6V)
鈥擵
TRIP2
Programmable down to 0.9V
鈥擜djust low voltage reset threshold voltages
using special programming sequence
鈥擱eset signal valid to V
CC
= 1V
鈥擬onitor two voltages or detect power fail
鈥?Battery Switch Backup
鈥?V
OUT
: 5mA to 50mA from V
CC
; or 250碌A(chǔ) from
V
BATT
鈥?Fault detection register
鈥?Selectable power-on reset timeout
(0.05s, 0.2s, 0.4s, 0.8s)
鈥?Selectable watchdog timer interval
(25ms, 200ms, 1.4s, off)
鈥?Debounced manual reset input
鈥?Low power CMOS
鈥?5碌A(chǔ) typical standby current, watchdog on
鈥?碌A(chǔ) typical standby current, watchdog off
鈥?碌A(chǔ) typical battery current in backup mode
鈥?4Kbits of EEPROM
鈥?6 byte page write mode
鈥擲elf-timed write cycle
鈥?ms write cycle time (typical)
鈥?Built-in inadvertent write protection
鈥擯ower-up/power-down protection circuitry
鈥擝lock lock protect 0 or 1/2, of EEPROM
鈥?400kHz 2-wire interface
鈥?2.7V to 5.5V power supply operation
鈥?Available packages
鈥?4-lead SOIC, TSSOP
鈥?鈥onitor Voltages: 5V to 1.6V
BLOCK DIAGRAM
鈥?Memory Security
鈥?Battery Switch Backup
鈥?V
OUT
5mA to 50mA
APPLICATIONS
鈥?Communications Equipment
鈥擱outers, Hubs, Switches
鈥擠isk arrays
鈥?Industrial Systems
鈥擯rocess Control
鈥擨ntelligent Instrumentation
鈥?Computer Systems
鈥擠esktop Computers
鈥擭etwork Servers
X40420/21
Standard V
TRIP1
Level
4.6V (+/-1%)
4.6V (+/-1%)
2.9V(+/-1.7%)
Standard V
TRIP2
Level
2.9V(+/-1.7%)
2.6V (+/-2%)
1.6V (+/-3%)
Suffix
-A
-B
-C
See 鈥淥rdering Information鈥?for more details
For Custom Settings, call Intersil.
DESCRIPTION
The X40420/21 combines power-on reset control,
watchdog timer, supply voltage supervision, and sec-
ondary supervision, manual reset, and Block Lock
鈩?/div>
protect serial EEPROM in one package. This combi-
nation lowers system cost, reduces board space
requirements, and increases reliability.
Applying voltage to V
CC
activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscilla-
tor to stabilize before the processor can execute code.
V
OUT
V2MON
+
V2 Monitor
Logic
V
TRIP2
V2FAIL
-
SDA
WP
Data
Register
Command
Decode Test
& Control
Logic
Fault Detection
Register
Status
Register
EEPROM
Array
Watchdog
and
Reset Logic
V
OUT
WDO
MR
RESET
X40420
SCL
V
OUT
V
CC
(V1MON)
+
V
CC
Monitor
Logic
System
Battery
Switch
V
TRIP1
-
Power-on,
Manual Reset
Low Voltage
Reset
Generation
RESET
X40421
BATT-ON
V
OUT
V
BATT
LOWLINE
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

X40420V14I-C 產(chǎn)品屬性

  • 95

  • 集成電路 (IC)

  • PMIC - 監(jiān)控器

  • -

  • 多壓監(jiān)控器

  • 2

  • 開路漏極，開路漏極

  • 高有效/低有效

  • 可調(diào)節(jié)/可選擇

  • 1.6V，2.9V

  • -40°C ~ 85°C

  • 表面貼裝

  • 14-TSSOP（0.173"，4.40mm 寬）

  • 14-TSSOP

  • 管件

X40420V14I-C相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    CPU Supervisor with 4kbit EEPROM
    INTERSIL
  • 英文版
    CPU Supervisor with 4Kbit EEPROM
    XICOR
  • 英文版
    CPU Supervisor with 4kbit EEPROM
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    CPU Supervisor with 4Kbit EEPROM
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    CPU Supervisor with 4kbit EEPROM
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  • 英文版
    Dual Voltage Monitor with Intergrated CPU Supervisor
    INTERSIL
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    Dual Voltage Monitor with Intergrated CPU Supervisor
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    Dual Voltage Monitor with Intergrated CPU Supervisor
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  • 英文版
    Dual Voltage Monitor with Intergrated CPU Supervisor
    INTERSIL [...
  • 英文版
    Dual Voltage Monitor with Intergrated CPU Supervisor
    INTERSIL [...
  • 英文版
    Dual Voltage Monitor with Intergrated CPU Supervisor
    INTERSIL
  • 英文版
    Dual Voltage Monitor with Intergrated CPU Supervisor
    INTERSIL [...
  • 英文版
    Dual Voltage Monitor with Integrated CPU Supervisor and Syst...
    INTERSIL
  • 英文版
    Dual Voltage Monitor with Integrated CPU Supervisor and Syst...
    XICOR
  • 英文版
    Dual Voltage Monitor with Integrated CPU Supervisor and Syst...
    INTERSIL [...
  • 英文版
    Dual Voltage Monitor with Integrated CPU Supervisor and Syst...
    XICOR [Xic...
  • 英文版
    Dual Voltage Monitor with Integrated CPU Supervisor and Syst...
    XICOR
  • 英文版
    Dual Voltage Monitor with Integrated CPU Supervisor and Syst...
    XICOR [Xic...
  • 英文版
    Triple Voltage Monitor with Integrated CPU Supervisor
    INTERSIL

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