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X28LC512P-15 Datasheet

  • X28LC512P-15

  • 3.3 Volt, Byte Alterable E2PROM

  • 19頁

  • XICOR   XICOR

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X28LC512/X28LC513
512K
X28LC512/X28LC513
3.3 Volt, Byte Alterable E
2
PROM
64K x 8 Bit
FEATURES
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Low V
CC
Operation: V
CC
= 3.3V
鹵
10%
Access Time: 150ns
Simple Byte and Page Write
鈥擲elf-Timed
鈥擭o Erase Before Write
鈥擭o Complex Programming Algorithms
鈥擭o Overerase Problem
Low Power CMOS:
鈥擜ctive: 25mA
鈥擲tandby: 150
碌
A
Software Data Protection
鈥擯rotects Data Against System Level
Inadvertant Writes
High Speed Page Write Capability
Highly Reliable Direct Write鈩?Cell
鈥擡ndurance: 10,000 Write Cycles
鈥擠ata Retention: 100 Years
Early End of Write Detection
鈥擠ATA Polling
鈥擳oggle Bit Polling
Two PLCC and LCC Pinouts
鈥擷28LC512
鈥擷28LC010 E
2
PROM Pin Compatible
鈥擷28LC513
鈥擟ompatible with Lower Density E
2
PROMs
DESCRIPTION
The X28LC512/513 is a low-power 64K x 8 E
2
PROM,
fabricated with Xicor鈥檚 proprietary, high performance,
floating gate CMOS technology. The X28LC512/513
features the JEDEC approved pinout for bytewide memo-
ries, compatible with industry standard EPROMS.
The X28LC512/513 supports a 128-byte page write
operation, effectively providing a 39碌s/byte write cycle
and enabling the entire memory to be written in less than
2.5 seconds. The X28LC512/513 also features
DATA
Polling and Toggle Bit Polling, system software support
schemes used to indicate the early completion of a write
cycle. In addition, the X28LC512/513 supports the Soft-
ware Data Protection option.
PIN CONFIGURATIONS
PLCC
A12
A15
NC
NC
VCC
WE
NC
PLASTIC DIP
NC
NC
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
X28LC512
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/04
I/O3
A11
A9
A8
A13
A14
NC
NC
NC
WE
VCC
NC
NC
NC
NC
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
TSOP
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
NC
NC
VSS
NC
NC
I/O2
I/O1
I/O0
A0
A1
A2
A3
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
30
32 31 29
54 3 2
1
6
28
7
8
9
10
11
12
13
14
27
26
25
24
23
22
15 16 17 18 19 20 21
I/O3
I/O4
I/O5
I/O6
X28LC512
(TOP VIEW)
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
X28LC512
I/O1
I/O2
VSS
3005 ILL F03
PLCC
A7
A12
A14
A15
VCC
WE
A13
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
30
32 31 29
54 3 2
1
6
28
7
27
26
8
X28LC513
25
9
(TOP VIEW)
24
10
11
23
12
22
13
15 16 17 18 19 20 21
14
I/O1
I/O2
VSS
NC
I/O3
I/O4
I/O5
3005 ILL F04.1
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
Characteristics subject to change without notice
3005 ILL F22.2
3005 ILL F02.1
漏 Xicor, Inc. 1991, 1995, 1996 Patents Pending
3005-3.2 8/5/97 T2/C0/D0 EW
1

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